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LTC1149CS Datasheet(PDF) 14 Page - Linear Technology |
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LTC1149CS Datasheet(HTML) 14 Page - Linear Technology |
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14 / 20 page ![]() 14 LTC1149 LTC1149-3.3/LTC1149-5 circuitry. Turning on the N-channel MOSFET when this fault is detected will then force the system fuse to blow. The N-channel MOSFET needs to be sized so it will safely handle this overcurrent condition. The typical delay from pulling the CT Pin 6 high to when the NGATE Pin 13 goes high is 250ns. Under shutdown conditions, the N-channel is held off and pulling Pin 6 high will not cause the output to be crowbarred. A small N-channel FET can be used as an interface between the overvoltage detect circuitry and the LTC1149 as shown in Figure 7. APPLICATIO S I FOR ATIO Figure 7. Output Crowbar Interface Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC1149 series. These items are also illustrated graphi- cally in the layout diagram of Figure 8. Check the following in your layout: 1. Are the signal and power grounds segregated? The LTC1149 signal ground Pin 11 must connect separately to the (–) plate of COUT. The other ground Pins 12 and 14 should return to the source of the N-channel MOSFET, anode of the Schottky diode and (–) plate of CIN, which should have as short lead lengths as possible. 2. Does the LTC1149 SENSE– Pin 8 connect to a point close to RSENSE and the (+) plate of COUT? In adjustable applications, the resistive divider R1, R2 must be connected between the (+) plate of COUT and signal ground. 3. Are the SENSE– and SENSE+ leads routed together with minimum PC trace spacing? The differential decou- pling capacitor between Pins 8 and 9 should be as close as possible to the LTC1149. Up to 100 Ω may be placed Figure 6. Suppressing Burst Mode Operation 25mV minimum current comparator threshold. This tech- nique is also useful for eliminating audible noise from certain types of inductors in high current (IOUT > 5A) applications when they are lightly loaded. An external offset is put in series with the SENSE– pin to subtract from the built-in 25mV offset. An example of this technique is shown in Figure 6. Two 100 Ω resistors are inserted in series with the leads from the sense resistor. With the addition of R3, a current is generated through R1 causing an offset of: VOFFSET = VOUT ) ) R1 R1 + R3 If VOFFSET > 25mV, the minimum threshold will be cancelled and Burst Mode operation is prevented from occurring. Since VOFFSET is constant, the maximum load current is also decreased by the same offset. Thus, to get back to the same IMAX, the value of the sense resistor must be lower: RSENSE ≈ 75mV IMAX To prevent noise spikes from erroneously tripping the current comparator, a 1000pF capacitor is needed across Pins 8 and 9. Output Crowbar An added feature to using an N-channel MOSFET as the synchronous switch is the ability to crowbar the output with the same MOSFET. Pulling the timing capacitor Pin 6 above 1.5V when the output voltage is greater than the desired regulated value, will turn on the N-channel MOSFET. A fault condition which causes the output voltage to go above a maximum value can be detected by external LTC1149 SENSE+ SENSE – 9 8 1000pF R1 100 Ω R2 100 Ω L RSENSE COUT R3 1149 F06 + LTC1149 5 6 VN2222LL CROWBAR ACTIVE WHEN CROWBAR = VIN OFF WHEN CROWBAR = GROUND 1149 F07 VCC CT |
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