LTC1196 datasheet(23/28 Pages) LINER

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LTC1196/LTC1198

APPLICATI

I FOR ATIO

3V VERSUS 5V PERFORMANCE COMPARISON

Table 1 shows the performance comparison between 3V

and 5V supplies. The power dissipation drops by a factor

of five when the supply is reduced to 3V. The converter

slows down somewhat but still gives excellent perfor-

mance on a 3V rail. With a 3V supply, the LTC1196

converts in 1.6

µs, samples at 450kHz, and provides a

500kHz linear-input bandwidth.

Dynamic accuracy is excellent on both 5V and 3V. The

ADCs typically provide 49.3dB of 7.9 ENOBs of dynamic

accuracy at both 3V and 5V. The noise floor is extremely

low, corresponding to a transition noise of less than

0.1LSB. DC accuracy includes

±0.5LSB total unadjusted

error at 5V. At 3V, linearity error is

±0.5LSB while total

unadjusted error increases to

±1LSB.

Table 1. 5V/3V Performance Comparison

LTC1196-1

PDISS

50mW

10mW

Max fSMPL

1MHz

383kHz

Min tCONV

600ns

1.6

µs

INL (Max)

0.5LSB

Typical ENOBs

7.9 at 300kHz

7.9 at 100kHz

Linear Input Bandwidth (ENOBs > 7)

1MHz

500kHz

LTC1198-1

PDISS

50mW

10mW

PDISS (Shutdown)

µW9µW

Max fSMPL

750kHz

287kHz

Min tCONV

600ns

1.6

µs

INL (Max)

0.5LSB

Typical ENOBs

7.9 at 300kHz

7.9 at 100kHz

Linear Input Bandwidth (ENOBs > 7)

1MHz

500kHz

APPLICATI

TYPICAL

PLD Interface Using the Altera EPM5064

The Altera EPM5064 has been chosen to demonstrate the

interface between the LTC1196 and a PLD. The EPM5064

is programmed to be a 12-bit counter and an equivalent

74HC595 8-bit shift register as shown in Figure 12. The

circuit works as follows: bringing ENA high makes the CS

output high and the EN input low to reset the LTC1196 and

disable the shift register. Bringing ENA low, the CS output

goes high for one CLK cycle with every 12 CLK cycles. The

inverted signal, EN, of the CS output makes the 8-bit data

available on the B0-B7] lines. Figures 13 and 14 show the

interconnection between the LTC1196 and EPM5064 and

the timing diagram of the signals between these two

devices. The CLK frequency in this circuit can run up to

fCLK(MAX) of the LTC1196.

1196/98 F12

DATA

CLK

12-BIT

CONVERTER

ENA

CLK

B0-B7

8-BIT

SHIFT REGISTER

ENA

CLK

DATA

B0-B7

Figure 12. An Equivalent Circuit of the EPM5064

Figure 13. Intefacing the LTC1196 to the Altera EPM5064 PLD

3, 14, 25, 36

EPM5064

CLK

1196/98 F13

VCC

–

DATA

9-13, 21,

31, 32, 43

CLK

ENA

–IN

GND

VCC

CLK

DOUT

+IN

LTC1196

VREF

µF

RESERVE PINS OF EPM5064:

2, 4-8,15-20, 22, 24, 26-30

LTC1196 Datasheet(PDF) 23 Page - Linear Technology

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