LTC1196 datasheet(24/28 Pages) LINER

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LTC1196/LTC1198

Figure 14. The Timing Diagram

APPLICATI

TYPICAL

the LTC1198 in Figure 15 can be 2.7V to 6V with fCLK =

5MHz. At 2.7V, fCLK = 5MHz will work at 25°C. See

Recommended Operating Conditions for limits over tem-

perature.

Hardware Description

The circuit works as follows: the LTC1198 clock line

controls the A/D conversion rate and the data shift rate.

Data is transferred in a synchronous format over DIN and

DOUT. The serial port of the TMS320C25 is compatible with

that of the LTC1198. The data shift clock lines (CLKR,

CLKX) are inputs only. The data shift clock comes from an

external source. Inverting the shift clock is necessary

because the LTC1198 and the TMS320C25 clock the input

data on opposite edges.

The schematic of Figure 15 is fed by an external clock

source. The signal is fed into the CLK pin of the LTC1198

directly. The signal is inverted with a 74HC04 and then

applied to the data shift clock lines (CLKR, CLKX). The

framing pulse of the TMS320C25 is fed directly to the CS

of the LTC1198. DX and DR are tied directly to DIN and

DOUT respectively.

Interfacing the LTC1198 to the TMS320C25 DSP

Figure 15 illustrates the interface between the LTC1198

8-bit data acquisition system and the TMS320C25 digital

signal processor (DSP). The interface, which is optimized

for speed of transfer and minimum processor supervi-

sion, can complete a conversion and shift the data in 4

µs

with fCLK = 5MHz. The cycle time, 4µs, of each conversion

is limited by maximum clock frequency of the serial port

of the TMS320C25 which is 5MHz. The supply voltage for

Figure 15. Interfacing the LTC1198 to the TMS320C25 DSP

1196/98 F15

5MHz CLK

CLKX

CLKR

FSR

FSX

CLK

LTC1198

TMS320C25

DIN

DOUT

CH0

CH1

140

210

280

350

420

490

560

630

700

770

840

910

980 1050 1120

DATA

CLK

TIME (ns)

1196/98 F14

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