LTC1421 datasheet(9/24 Pages) LINER

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LTC1421/LTC1421-2.5

APPLICATIONS INFORMATION

PWRGD and RESET

The LTC1421 uses a 1.232V bandgap reference, internal

resistive divider and a precision voltage comparator to

monitor VOUTLO (Figure 6).

The reset threshold voltage for VOUTLO is determined by

the FB pin connection as summarized in Table 1.

When VOUTLO drops below its reset threshold, the com-

parator output goes high, and PWRGD is immediately

pulled low (time point 2). After a 32

µs delay, RESET is

pulled low. The RESET delay allows the PWRGD signal to

be used as an early warning that a reset is about to occur.

If the PWRGD signal is used as a interrupt input to a

microprocessor, a short power-down routine can be run

before the reset occurs.

If VOUTLO rises above the reset threshold for less than

200ms, the PWRGD output will trip, but the RESET output is

not affected (time point 3). If VOUTLO drops below the reset

threshold for less than 32

µs,thePWRGDoutputwilltrip,but

again the RESET output will not be affected (time point 5).

Voltage Comparator

The uncommitted voltage comparator (COMP2) can be

used to monitor output voltages other than VOUTLO. Figure

8a shows how the comparator can be used to monitor a

12V supply (VOUTHI), while the 5V supply (VOUTLO) gener-

ates a reset when it dips below 4.65V. When the 12V

supply drops below 10.8V, COMPOUT will pull low. The FB

pin is left floating.

Figure 8b shows how the comparator can be used to

monitor the 5V supply (VOUTHI) while the 3.3V supply

(VOUTLO) generates a reset when it dips below 2.9V. When

the 5V supply drops below 4.65V, COMPOUT will pull low.

The FB pin is tied to VOUTLO.

Figure 6. Supply Monitor Block Diagram

–

VCCLO

VOUTLO

1421 F06

1.232V

µA

26.7k

PWRGD

RESET

COMP1

RESET

TIMING

REF

73.5k

71.5k

VOUTLO

PWRGD

RESET

µs

200ms

< 200ms

200ms

1421 F07

<64

µs

Table 1

FEEDBACK PIN

VOUTLO RESET VOLTAGE

Floating

4.65V

VOUTLO

2.90V

GND

5.88V

When the VOUTLO voltage rises above its reset threshold

voltage, the comparator output goes low, and PWRGD is

immediately pulled high to VCCLO by a weak pull-up

current source or external resistor (Figure 7, time points

1 and 4). After a 200ms delay, RESET is pulled high. The

weak pull-up current source to VCCLO on PWRGD and

RESET have a series diode so the pins can be pulled above

VCCLO by an external pull-up resistor without forcing

current back into VCCLO.

Figure 7. Power Monitor Waveforms

Figure 8a. Monitor 12V, Reset 5V at 4.65V

1421 F08a

10k

107k

13.7k

12V

–

VCCLO

1.232V

LTC1421

µA

26.7k

COMP1

COMP2

RESET

TIMING

73.5k

107k

71.5k

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