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LTC1421 Datasheet(PDF) 15 Page - Linear Technology |
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LTC1421 Datasheet(HTML) 15 Page - Linear Technology |
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15 / 24 page ![]() 15 LTC1421/LTC1421-2.5 APPLICATIONS INFORMATION time point 2). Pulses less than 20ms on POR are ignored. CPON goes low. Both GATEHI and GATELO will be actively pulled down to GND. When VOUTLO drops below its reset threshold voltage, PWRGD will immediately pull low (time point 3) followed by RESET and DISABLE 32 µs later (time point 4). Both supplies will be discharged to ground and stay there until POR is pulled high. The circuit breaker can be reset by pulling POR low. After POR is low for more than 20ms, the chip will immediately try to power up the supplies. Circuit Breaker Timing The waveforms for the circuit when a short occurs on either supply during board insertion are shown in Figure 16. Time points 1 to 4 are the same as the board insertion example, but at time point 5, a short circuit is detected on one of the supplies. The charge pumps are immediately turned off, the outputs VOUTHI and VOUTLO are actively pulled to GND and the CPON and FAULT pins are pulled low. At time point 6, the circuit breaker is reset by pulling POR low. After POR has been low for 20ms (time point 7), CPON and FAULT are pulled high, the 20 µA reference current is connected to RAMP and the charge pumps are enabled. VOUTHI and VOUTLO ramp up at a controlled rate. When VOUTLO has exceeded its reset threshold, the PWRGD signal is pulled high (time point 8). After a 200ms delay, RESET is pulled high and DISABLE goes low. Figure 16. Circuit Breaker Timing VCCLO 12 3 4 5 6 VCCHI DISABLE CON1 78 9 CON2 CPON PWRGD VTH1 1421 F16 VOUTHI GATEHI GATELO VOUTLO RESET FAULT POR 20ms 20ms 200ms |
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