LTC1421 datasheet(16/24 Pages) LINER

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LTC1421/LTC1421-2.5

APPLICATIONS INFORMATION

VCCLO

VCCHI

DISABLE

CON1

CON2

CPON

PWRGD

VTH2

1421 F17

VOUTHI

GATEHI

GATELO

VOUTLO

RESET

FAULT

POR

µs

Figure 17. Board Removal Timing

Board Removal Timing

When the board is removed from the host, the sequence

happens in reverse (Figure 17). Since CON1 and CON2 are

the shortest pins, they break connection first and are

internally pulled high (time point 1). The charge pumps are

turned off, CPON is pulled low. VOUTLO and VOUTHI are

actively pulled down. When VOUTLO falls below its reset

threshold (time point 2) PWRGD is pulled low. To allow

time for power fail information to be stored in nonvolatile

memory, the falling edge of RESET (time point 3) is

delayed by 32

µs from the falling edged of PWRGD.

Finally, the input supply pins VCCHI and VCCLO break

contact (time point 4). If staggered pins are not used, the

board may be powered down prior to removal by switch-

ing the POR pin to ground with a toggle switch.

LTC1421 Datasheet(PDF) 16 Page - Linear Technology