7

LTC1599

CLVL (Pin 10): Clear Level. CLVL = 0, selects reset to zero

code. CLVL = 1, selects reset to midscale code. Normally

hardwired to a logic high or a logic low.

LD (Pin 11): DAC Digital Input Load Control Input. When

LD is taken to a logic low, data is loaded from the input

register into the DAC register, updating the DAC output.

WR (Pin 12): DAC Digital Write Control Input. When WR

is taken to a logic low, data is loaded from the 8 digital input

pins into the 16-bit wide input register. The MLBYTE pin

determines whether the MSB or LSB byte is loaded.

MLBYTE (Pin 13): MSB or LSB Byte Select. When MLBYTE

is taken to a logic low and WR is taken to a logic low, data

is loaded from the 8 digital input pins into the first 8 bits

of the 16-bit wide input register. When MLBYTE is taken to

a logic high and WR is taken to a logic low, data is loaded

from the 8 digital input pins into the 8 MSB bits of the input

register.

D7 to D3 (Pins 14 to 18): Digital Input Data Bits.

DGND (Pin 19): Digital Ground. Tie to ground.

Requires a bypass capacitor to ground.

D2 to D0 (Pins 21 to 23): Digital Input Data Bits.

CLR (Pin 24): Digital Clear Control Function for the DAC.

When CLR and CLVL are taken to a logic low, the DAC

output and all internal registers are set to zero code. When

CLR is taken to a logic low and CLVL is taken to a logic high,

the DAC output and all internal registers are set to midscale

code.

REF (Pin 1): Reference Input. Typically

±10V, accepts up

to

±25V. In 2-quadrant mode, this pin is the reference

input. In 4-quadrant mode, this pin is driven by external

inverting reference amplifier.

R2 (Pin 2): 4-Quadrant Resistor R2. Typically

±10V,

accepts up to

±25V. In 2-quadrant operation, connect this

pin to ground. In 4-quadrant mode tie to the REF pin and

to the output of an external amplifier. See Figures 1 and 3.

Resistors R1 and R2. Normally tied to the inverting input

of an external amplifier in 4-quadrant operation, otherwise

connect this pin to ground. See Figures 1 and 3. The ab-

solute maximum voltage range on this pin is – 0.3V to 12V.

R1 (Pin 4): 4-Quadrant Resistor R1. Typically

±10V,

accepts up to

±25V. In 2-quadrant operation connect this

Figures 1 and 3.

±10V, accepts up to ±25V. In 2-quadrant operation, tie to

of the current to voltage converter op amp. Typically

swings

input of the current to voltage converter op amp.

mally tied to ground.

mally tied to ground.

TRUTH TABLE

Table 1

CONTROL INPUTS

CLR

WR

MLBYTE

LD

REGISTER OPERATION

0

X

X

X

Reset Input and DAC Registers to Zero Scale When CLVL = 0 and Midscale When CLVL = 1

1

0

1

Load the LSB Byte of the Input Register with All 8 Data Bits

1

1

1

Load the MSB Byte of the Input Register with All 8 Data Bits

11

X

Load the DAC Register with the Contents of the Input Register

1

1

X

1

No Register Operation

1

X

Flow-Through Mode. The DAC Register and the Selected Input Register Are Transparent. The Unselected Input

Register Retains Its Previous Data Byte. Note Only One Byte Is Transparent at a Time, the Selected Byte Being

Determined By the Logic Value of MLBYTE Prior to WR Being Pulsed Low.