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LTC1703 Datasheet(PDF) 18 Page - Linear Technology |
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LTC1703 Datasheet(HTML) 18 Page - Linear Technology |
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18 / 36 page ![]() 18 LTC1703 The two sides of the LTC1703 run off a single master clock and are wired 180 ° out of phase with each other to significantly reduce the total capacitance/ESR needed at the input. Assuming 100mV of ripple and 10A output current, we needed an ESR of 0.01 Ω and 4.7A ripple current capability for one side. Now, assume both sides are running simultaneously with identical loading. If the two sides switched in phase, all the loading conditions would double and we’d need enough capacitance for 9.4ARMS and 0.005Ω ESR. With the two sides out of phase, the input current is 4.8ARMS—barely larger than the single case (Figure 7)! The peak current deltas are still only 10A, requiring the same 0.01 Ω ESR rating. As long as the capacitor we chose for the single side application can support the slightly higher 4.8ARMS current, we can add the second channel without changing the input capacitor at all. As a general rule, an input bypass capacitor capable of supporting the larger output current channel can sup- port both channels running simultaneously (see the 2-Phase Operation section for more information). Details on how to calculate the maximum RMS input current can be found in Application Note 77. Tantalum capacitors are a popular choice as input capaci- tors for LTC1703 applications, but they deserve a special caution here. Generic tantalum capacitors have a destruc- tive failure mechanism when they are subjected to large RMS currents (like those seen at the input of a LTC1703). Figure 7. Current Waveforms At the same time, the input supply needs to supply several amps of current without excessive voltage drop. The input supply must have regulation adequate to prevent sudden load changes from causing the LTC1703 input voltage to dip. In most typical applications where the LTC1703 is generating a secondary low voltage logic supply, all of these input conditions are met by the main system logic supply when fortified with an input bypass capacitor. INPUT BYPASS CAPACITOR A typical LTC1703 circuit running from a 5V logic supply might provide 1.6V at 10A at one of its outputs. 5V to 1.6V implies a duty cycle of 32%, which means QT is on 32% of each switching cycle. During QT’s on-time, the current drawn from the input equals the load current and during the rest of the cycle, the current drawn from the input is near zero. This 0A to 10A, 32% duty cycle pulse train adds up to 4.7ARMS at the input. At 550kHz, switching cycles last about 1.8 µs—most system logic supplies have no hope of regulating output current with that kind of speed. A local input bypass capacitor is required to make up the difference and prevent the input supply from dropping drastically when QT kicks on. This capacitor is usually chosen for RMS ripple current capability and ESR as well as value. The input bypass capacitor in an LTC1703 circuit is common to both channels. Consider our 10A example case with the other side of the LTC1703 disabled. The input bypass capacitor gets exercised in three ways: its ESR must be low enough to keep the initial drop as QT turns on within reason (100mV or so); its RMS current capability must be adequate to withstand the 4.7ARMS ripple current at the input and the capacitance must be large enough to maintain the input voltage until the input supply can make up the difference. Generally, a capacitor that meets the first two parameters will have far more capacitance than is required to keep capacitance-based droop under control. In our example, we need 0.01 Ω ESR to keep the input drop under 100mV with a 10A current step and 4.7ARMS ripple current capacity to avoid overheating the capacitor. These requirements can be met with multiple low ESR tantalum or electrolytic capacitors in parallel, or with a large mono- lithic ceramic capacitor. 0 10A 32% 68% 0 10A 32% 18% 18% 18% 32% –3.2A 0 6.8A 32% 68% QT CURRENT, SIDE 1 ONLY (FOR 1-PHASE, 2 SIDES: MULTIPLY CURRENT BY 2) CURRENT IN CIN, SIDE 1 ONLY ICIN = 4.66ARMS, (1-PHASE, 2 SIDES: ICIN = 9.3ARMS) CURRENT IN CIN, BOTH SIDES EQUAL LOAD ICIN = 4.8ARMS QT1 CURRENT QT2 CURRENT BOTH SIDES EQUAL LOAD 2-PHASE OPERATION –6.4A 0 3.6A 32% 18% 1703 F07 32% APPLICATIO S I FOR ATIO |
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