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LTC1929

The duty factors when the peak RMS input current occurs

is at D = 0.25 and D = 0.75 according to Figure 4. Calculate

the worst-case required RMS current rating at the input

voltage that produces a duty cycle nearest to the peak.

CIN will require an RMS current rating of:

C requiredI

RMS

() −− −













476

The output capacitor ripple current is calculated by using

the inductor ripple already calculated for each inductor

and multiplying by the factor obtained from Figure 3 along

with the calculated duty factor. The output ripple in con-

tinuous mode will be highest at the maximum input

voltage since the duty factor is < 50%. The maximum

output current ripple is:

∆

D F

kHz

COUT

OUT

COUTMAX

OUTRIPPLE

RMS

=−

















= () µ

()

−









=Ω

()=

033

066

310

054

097

194

%. .

An alternate calculation just uses the equation for output

ripple current at D = 1.8V/5.5 = 0.33:

∆I

kHz

RIPPLE

OUTRIPPLE

RMS

()

−

() −

()

−

() +













=Ω

()=

21 8

310

1 2 033 1 033

12 0 33

099

197

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

LTC1929. These items are also illustrated graphically in

the layout diagram of Figure 11. Check the following in

your layout:

1) Are the signal and power grounds segregated? The

LTC1929 signal ground pin should return to the (–) plate

of COUT separately. The power ground returns to the

sources of the bottom N-channel MOSFETs, anodes of the

Schottky diodes, and (–) plates of CIN, which should have

as short lead lengths as possible.

2) Does the LTC1929 VOS+ pin connect to the (+) plate(s)

of COUT? Does the LTC1929 VOS– pin connect to the (–)

plate(s) of COUT? The resistive divider R1, R2 must be

connected between the VDIFFOUT and signal ground and

any feedforward capacitor across R1 should be as close as

possible to the LTC1929.

3) Are the SENSE – and SENSE + leads routed together with

minimum PC trace spacing? The filter capacitors between

SENSE + and SENSE– pin pairs should be as close as

possible to the LTC1929. Ensure accurate current sensing

with Kelvin connections.

4) Do the (+) plates of CIN connect to the drains of the

topside MOSFETs as closely as possible? This capacitor

provides the AC current to the MOSFETs. Keep the input

current path formed by the input capacitor, top and bottom

MOSFETs, and the Schottky diode on the same side of the

PC board in a tight loop to minimize conducted and

radiated EMI.

5) Is the INTVCC 1µF ceramic decoupling capacitor con-

nected closely between INTVCC and the power ground pin?

This capacitor carries the MOSFET driver peak currents. A

small value is used to allow placement immediately adja-

cent to the IC.

6) Keep the switching nodes, SW1 (SW2), away from

sensitive small-signal nodes. Ideally the switch nodes

should be placed at the furthest point from the LTC1929.

7) Use a low impedance source such as a logic gate to drive

the PLLIN pin and keep the lead as short as possible.

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