UPD77017GC datasheet(22/60 Pages) NEC

22 / 60 page

µPD77015, 77017, 77018

2.4.3

Data Memory Addressing

There are following two types of data memory addressing.

• Direct addressing

The address is specified in the instruction field.

• Indirect addressing

The address is specified by the data pointer (DP). DP can get a bit reverse before addressing. It can

update the DP value after accessing data memory.

2.5

On-chip Peripheral Circuit

The

µPD77017 includes serial interface, host interface, general input/output ports and wait cycle registers.

They are mapped in both X and Y memory areas, and are accessed as memory mapped I/O by the

µPD77017

CPU.

2.5.1

Serial Interface Outline

The

µPD77017 has 2 channel serial interfaces. Serial I/O clock must be provided from external. Frame length

can be programmed independently to be 8 bits or 16 bits. MSB first or LSB first can also be selected. Data is

input/output by hand shaking for an external device, and by interrupts, polling or wait function in internal.

2.5.2

Host Interface Outline

The

µPD77017 has 8 bits parallel ports as host interface to input/output data to and from host CPU and DMA

controller. When an external device accesses host interface, HA0 and HA1 pins; which are host address input

pins; specifies bit 15 to bit 8 and bit 7 to bit 0. The

µPD77017 includes 3 registers consisting of 16 bits, which

are dedicated for input data, output data and status. The

µPD77017 has three types of interface method for

internal and external data; interrupts, polling and wait function.

2.5.3

General Input/output Ports Outline

General input/output ports consist of 4 bits. User can set each port as input or output. The

µPD77017 includes

two registers. One is 4 bits register for input/output data, and the other is 16 bits for control.

2.5.4

Wait Cycle Register

The wait cycle registers consist of 16 bits. It is used to set wait cycle number when external memory is

accessed. When external data memory area (C000H - FFFFH) is accessed, 0, 1, 3, or 7 wait cycle can be set.

When external data memory area is accessed, wait cycle can be also set by WAIT pin.

UPD77017GC Datasheet(PDF) 22 Page - NEC

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