UPD77112 datasheet(20/80 Pages) NEC

20 / 80 page

Data Sheet U12801EJ4V0DS00

µµµµPD77110, 77111, 77112

2. FUNCTION OUTLINE

2.1 Program Control Unit

This unit is used to execute instructions, and control branching, loops, interrupts, the clock, and the standby mode

of the DSP.

2.1.1 CPU control

A three-stage pipeline architecture is employed and almost all the instructions, except some instructions such as

branch instructions, are executed in one system clock.

2.1.2 Interrupt control

Interrupt requests input from external pins (INT1 through INT4) or generated by the internal peripherals (serial

interface and host interface) are serviced.

The interrupt of each interrupt source can be enabled or disabled.

Multiple interrupts are also supported.

2.1.3 Loop control task

A loop function without any hardware overhead is provided. A loop stack with four levels is provided to support

multiple loops.

2.1.4 PC stack

A 15-level PC stack that stores the program counter supports multiple interrupts and subroutine calls.

2.1.5 PLL

A PLL is provided as a clock generator that can multiply or divide an external clock input to supply an operating

clock to the DSP. The multiplication and division ratio are set as follows:

•

µPD77110: A multiple of ×1 to ×8 is specified by an external pin (division ratio is fixed).

•

µPD77111 and 77112: A multiple of ×1 to ×16 or a division ratio of 1/1 to 1/16 can be set by a mask option.

Two standby modes are available for lowering the power consumption while the DSP is not in use.

•

HALT mode : Set by execution of the HALT instruction. The current consumption drops to several mA. The

normal operation mode is recovered by an interrupt or hardware reset.

•

STOP mode: Set by execution of the STOP instruction. The current consumption drops to several 10

µA. The

normal operation mode is recovered by hardware reset or WAKEUP pin

Note.

Note If the WAKEUP function is activated by mask option

2.1.6 Instruction memory

The capacity and type of the memory differ depending on the model of the DSP.

64 words of the instruction RAM are allocated to interrupt vectors.

A boot-up ROM that boots up the instruction RAM is provided, and the instruction RAM can be initialized or

rewritten by self boot (boot from the internal data ROM or external data space) or host boot (boot via host interface).

•

µPD77110: 35.5K-word RAM

•

µPD77111, 77112: 1K-word RAM and 31.75K-word ROM

UPD77112 Datasheet(PDF) 20 Page - NEC

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