L2340 datasheet(2/11 Pages) LODEV

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DEVICES INCORPORATED

L2340

Digital Synthesizer

Special Arithmetic Functions

08/16/2000–LDS.2340-E

FM PM Configuration

00 No accumulation (normal operation)

01 PM accumulator path enabled

10 FM accumulator path enabled

11 Logical OR of PM and FM (Nonsensical)

TABLE 2. ACCUMULATOR CONTROL

SIGNAL DEFINITIONS

Power

Vcc and GND

+5V power supply. All pins must be

connected.

Clock

CLK — Master Clock

The rising edge of CLK strobes all

enabled registers.

Inputs

AM14-0 — Amplitude Modulation Data

Input

AM14-0 is the 15-bit Amplitude

Modulation Data input port. AM14-0

is latched on the rising edge of CLK.

PH31-0 — Phase Angle Data Input

PH31-0 is the 32-bit Phase Angle Data

input port. Input phase accumulators

are loaded through this port into

registers enabled by ENP1-0. PH31-0 is

latched on the rising edge of CLK.

Outputs

I15-0 — x-coordinate Data Output

I15-0 is the 16-bit Cartesian x-coordi-

nate Data output port. When OEI is

HIGH, I15-0 is forced into the high-

impedance state. I15 is forced HIGH if

OBIQ is LOW.

Q15-0 — y-coordinate Data Output

Q15-0 is the 16-bit Cartesian y-coordi-

nate Data output port. When OEQ is

HIGH, Q15-0 is forced into the high-

impedance state. Q15 is forced HIGH

if OBIQ is LOW.

Controls

ENA — Amplitude Modulation Data

Input Enable

When ENA is HIGH, AM is latched

into the input register on the rising

edge of clock. When ENA is LOW, the

value stored in the register is un-

changed.

ENP1-0 — Phase Modulation Data Input

Control

ENP1-0 is the 2-bit Phase Modulation

Data Input Control that determines

one of the four modes shown in Table

1. ‘M’ is the Modulation Register and

‘C’ is the Carrier Register as shown in

the Functional Block Diagram.

TABLE 1. REGISTER OPERATION

L2340 FUNCTIONAL BLOCK DIAGRAM

I15-0

Q15-0

TRANSFORM

PROCESSOR

OEI

OEQ

OBIQ

AM14-0

PH31-0

ENA

ENP1-0

REQUIRES 18 CYCLES TO COMPLETE AND IS FULLY PIPELINED

ENP1-0 Configuration

0 0

No registers enabled, current data held

0 1

M register input enabled, C data held

1 0

C register input enabled, M data held

1 1

M register = 0, C register input enabled

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