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LF3347 Datasheet(PDF) 2 Page - LOGIC Devices Incorporated |
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LF3347 Datasheet(HTML) 2 Page - LOGIC Devices Incorporated |
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2 / 10 page  DEVICES INCORPORATED LF3347 High-Speed Image Filter with Coefficient RAM 2 Video Imaging Products 08/16/2000–LDS.3347-G with an image resampling se- quencer. Larger kernels or more complex functions can be realized by utilizing multiple devices. Unrestricted access to all data ports and addressable coefficient banks provides the LF3347 with considerable flexibility in applica- tions such as digital filters, adap- tive FIR filters, mixers, and other similar systems requiring high- speed processing. SIGNAL DEFINITIONS Power VCC and GND +3.3 V power supply. All pins must be connected. Clocks CLK — Master Clock The rising edge of CLK strobes all enabled registers. CCCLK — Coefficient/Control Clock When LD is LOW, the rising edge of CCCLK latches data on CC11-0 into the device. Inputs D111-0 – D411-0 — Data Input D1–D4 are the 12-bit registered data input ports. Data is latched on the rising edge of CLK. A7-0 — Row Address A7-0 determines which row in the coefficient banks feed data to the multipliers. A7-0 is latched on the rising edge of CLK. When a new row address is loaded into the row address register, data from the coefficient banks will be latched into the multiplier input registers on the next rising edge of CLK. CC11-0 — Control/Coefficient Data Input CC11-0 is used to load data into the coefficient banks and control regis- ters. Data present on CC11-0 is latched on the rising edge of CCCLK when LD is LOW. Outputs S15-0 — Data Output S15-0 is the 16-bit registered data output port. Controls ENB1–ENB4 — Data Input Enables The ENBN (N = 1, 2, 3, or 4) inputs allow the DN registers to be updated on each clock cycle. When ENBN is LOW, data on DN11-0 is latched into the DN register on the rising edge of CLK. When ENBN is HIGH, data on DN11-0 is not latched into the DN register and the register contents will not be changed. ENBA — Row Address Input Enable The ENBA input allows the row address register to be updated on each clock cycle. When ENBA is LOW, data on A7-0 is latched into the row address register on the rising edge of CLK. When ENBA is HIGH, data on A7-0 is not latched into the row address register and the register contents will not be changed. OE — Output Enable When OE is LOW, S15-0 is enabled for output. When OE is HIGH, S15-0 is placed in a high-impedance state. FIGURE 1. INPUT FORMATS TABLE 1. OUTPUT FORMATS SHIFT4-0 S15 S14 S13 · · · S8 S7 · · · S2 S1 S0 00000 F15 F14 F13 · · · F8 F7 · · · F2 F1 F0 00001 F16 F15 F14 · · · F9 F8 · · · F3 F2 F1 00010 F17 F16 F15 · · · F10 F9 · · · F4 F3 F2 · · · · ·· ·· · · · · · ·· ·· · · · · · ·· ·· · 01110 F29 F28 F27 · · · F22 F21 · · · F16 F15 F14 01111 F30 F29 F28 · · · F23 F22 · · · F17 F16 F15 10000 F31 F30 F29 · · · F24 F23 · · · F18 F17 F16 11 10 9 2 1 0 –2 0 (Sign) 2 –1 2–2 2 –9 2 –10 2–11 11 10 9 2 1 0 –2 0 (Sign) 2 –1 2–2 2 –9 2–10 2–11 11 10 9 2 1 0 –2 11 (Sign) 2 10 2 9 2 2 2 1 2 0 11 10 9 2 1 0 –2 11 (Sign) 2 10 2 9 2 2 2 1 2 0 Fractional Two's Complement Integer Two's Complement Data Coefficient |
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