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ATM QUAD SONET FRAMER

Document No.

S12953EJ4V0DS00 (4th edition)

Date Published

January 1999 NS

CP(K)

Printed in Japan

©NEC Corporation 1997,1999

MOS INTEGRATED CIRCUIT

DATA SHEET

The

µPD98411 NEASCOT-P40 is one of ATM-LAN LSIs and provides the functions of the TC sublayer of the

SONET/SDH-base physical layer of the ATM protocol specified by the ATM Forum.

Its main functions include a

transmission function to map an ATM cell passed from an ATM layer to the payload of 155M-bps SONET STS-

3c/SDH STM-1 frame and transmit the cell to the PMD (Physical Media Dependent) sublayer of the physical layer,

and a reception function to separate the overhead and ATM cell from the data string received from the PMD device

and transmit the ATM cell to the ATM layer.

The

µPD98411 NEASCOT-P40 combines these transmission

/reception functions into a port function that is realized as a single 4-port LSI chip.

This LSI is ideally suited for

use in the ATM hubs, ATM switches, and other equipment used to configure an ATM network.

In addition, the

µPD98411 also has a clock recovery function for each port to extract synchronous clock for

reception of receive data from the bit stream, and a clock synthesis function to generate a clock for transmission.

For the details of functional description, refer to the following user's manual.

µµµµPD98411 User's Manual : S12736E

FEATURES

• Incorporates an ATM user network interface TC sublayer function for four channels.

• Conforms to ATM FORUM UNI v3.1.

• Incorporates four clock recovery PLLs and one clock synthesizer PLL.

• Conforms to ATM FORUM UTOPIA Level 2 v1.0.

•

ATM layers can be selected from the multi-PHY interface (up to 800 Mbps) in several different modes.

Single 16-bit

1TCLAV/1RCLAV (Cell Available signal mode)

Single 8-bit

Direct Status Indication mode

Dual 8-bit

Multiplexed Status Polling mode

•

A management interface can be set to either of two modes.

RD-WR-RDY style (Intel-compatible mode)

DS-R/W-ACK style (Motorola-compatible mode)

• The line-side PMD interface accepts a P-ECL level input.

• Supports a loopback function.

• Supports a pseudo error generation frame transmission function.

• Incorporates one general input port per channel and three output ports (each able to drive an LED) per

channel.

• Supports JTAG boundary scan test (IEEE 1149.1).