UPD98411 datasheet(19/36 Pages) NEC

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Data Sheet

S12953EJ4V0DS00

µµµµPD98411

1.3

Management Interface

Pin Name

Pin No.

I/O Level

I/O

Function

BMODE

CMOS

Mode selection input.

This pin input is used to select the mode of the management

interface.

BMODE=:

1: Selects <RD_B, WR_B, RDY_B> as the pin function.

0: Selects <DS_B, R/W_B, ACK_B> as the pin function.

MADD[8:0]

26-34

CMOS

Address input.

9-bit addresses for inputting internal register addresses.

MD[7:0]

36-39

42-45

CMOS

I/O

3-state

8-bit data buses for reading/writing internal register data.

CS_B

CMOS

Chip select signal input.

When at low level, access to internal registers is enabled.

DS/RD_B

CMOS

Data strobe signal input or read signal input.

The function of this pin varies depending on the management

interface mode selected for the BMODE pin input.

BMODE =0: Functions as data strobe signal DS_B

BMODE =1: Function as RD_B selecting the read access

RW/WR_B

CMOS

Read/write signal input or write signal input.

The function of this pin varies depending on the management

interface mode selected for the BMODE pin input. When

BMODE=0, the pin functions as Read/Write control signal

R/W_B.

R/W_B= High:

Read cycle

Low:

Write cycle

When BMODE=1, the pin functions as WR_B selecting Write for

internal registers.

ACK/RDY_B

CMOS

3-state

Data acknowledge signal output or ready signal output.

Outputs acknowledge and ready signals which accept the

Read/Write cycle for internal registers.

PHINT3_B-

PHINT0_B

149-152

CMOS

Interrupt signal output.

These signals inform the host that an interrupt factor has

occurred. Two modes are available for this purpose: one which

indicates an interrupt factor for four ports using the PHINT0_B

signal and the other which uses four pins PHINT0-PHINT3 to

indicate an individual interrupt for each port. Port 0 corresponds

to the PHINT0_B pin; and Port 3 to PHINT3_B.

RESET_B

153

CMOS

System reset signal input.

Initializes the

µPD98411. This input signal should be kept low for

µs or more. Especially, in case of the power on, above-

mentioned pulse width must be kept after the supply voltage

reaches equal to or more than 90% at least. When the

RESET_B signal is input, the clock must be input at REFCLK pin.

UPD98411 Datasheet(PDF) 19 Page - NEC

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