UPD98411 datasheet(13/36 Pages) NEC

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Data Sheet

S12953EJ4V0DS00

µµµµPD98411

1. PIN FUNCTIONS

1.1

PMD Interface

(1/3)

Pin Name

Pin No.

I/O Level

I/O

Function

RDIT3-

RDIT0

105, 94,

85, 74

P-ECL

True(+)

RDIC3-

RDIC0

104, 93,

84, 73

P-ECL

Complement(-)

Receive serial data input.

Refers to the differential input of the P-ECL level.

TDOT3-

TDOT0

98, 89,

78, 69

P-ECL

True(+)

TDOC3-

TDOC0

99, 90,

79, 70

P-ECL

Complement(-)

Transmit serial data output.

Refers to the differential output of the P-ECL level. To the transmit

clock.

SD3-SD0

119-116

CMOS

Line signal detection signal input.

Refers to the pins for inputting the SD (Signal Detect) signal of

line transceivers (such as optical modules). If this signal goes low,

this port detects LOS.

High: Normal

Low: LOS state

REFCLK

CMOS

System clock (19.44MHz) input.

Used as the source clock for the internal synthesizer PLL/clock

recovery PLL and register operation.

REFCLK-2nd

CMOS

Second system clock (19.44MHz) input.

Refers to the pin for inputting the second source clock of the

internal synthesizer PLL. This pin is not used if it is unnecessary

to switch the source clock of the synthesizer PLL. The CSSC

REFCLK-2nd clocks to use as the source block. The REFCLK

input is selected as the default. Even when REFCLK-2nd is used

as the source clock of the synthesizer PLL, REFCLK is used for

clock.

RXFP

126

CMOS

Receive frame pulse output (8kHz).

The pulse signal is output synchronously with the start of the

receiving frame. The pulse signal is 1 cycle of the RCL clock in

length.

The internal FPMSK register (address: 07CH) is used to select

which of the four ports will output the pulse synchronous to the

receiving frame. No port is selected as the default; therefore,

using the default will result in no output.

Transmit synthesizer

PLL clock

155.52MHz

transmit clock

REF_cnt bit

REFCLK

REFCLK_2nd

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