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RF2054

DS120320

7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical

support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com.

PLL Lock Detect

The lock detect function is a window detector, indicating an out of lock condition when the VCO tuning voltage is outside of a

certain voltage range. When out of lock then the LOCK bit will be high, bit 1 in the read back register RB1. It is possible that

when an out of lock is indicated the PLL is still locked, but the tuning voltage has drifted outside of the window.

There are two windows for the lock detector set by LD_LEV, bit 14 in register CFG1. The following are the typical tuning voltage

ranges for the lock detect circuit measured with +2.2V supply voltage to the RF2054:

LD_LEV = 0: 0.55V to 1.55V (narrow window)

LD_LEV = 1: 0.35V to 1.75V (wide window)

Phase Detector and Charge Pump

The chip provides a current output to drive an external loop filter. An on-chip operational amplifier can be used to design an

active loop filter or a passive design can be implemented. The maximum charge pump output current is set by the value con-

tained in the P1_CP_DEF/P2_CP_DEF field and CP_LO_I.

In the default state (P1_CP_DEF/P2_CP_DEF = 31 and CP_LO_I = 0) the charge pump current (ICPset) is 120

A. If CP_LO_I is

set to 1 this current is reduced to 30

A.

The charge pump current can be altered by changing the value of P1_CP_DEF/P2_CP_DEF. The charge pump current is

defined as:

ICP= ICPset*CP_DEF / 31

If automatic loop bandwidth correction is enabled the charge pump current is set by the calibration algorithm based upon the

VCO gain. For more information on the VCO gain calibration, which is disabled by default, please refer to the RF205x Calibra-

tion User Guide.

The phase detector will operate with a maximum input frequency of 26MHz.

Loop Filter

The PLL may be designed to use an active or a passive loop filter as required. The internal configuration of the chip is shown

below. If the CFG1:LF_ACT bit is asserted high, the op-amp will be enabled. If the CFG1:LF_ACT bit is asserted low, the internal

op-amp is disabled and a high impedance is presented to the LFILT1 pin. The RF205x Programming Tool software can assist

with loop filter designs. Because the op-amp is used in an inverting configuration in active mode, when the passive loop filter

mode is selected the phase-detector polarity should be inverted. For active mode, CFG1:PDP = 1, for passive mode, CFG1:PDP

= 0.

+

-

LFILT1

LFILT2

LFILT3

To VCO Tuning

LF_ACT=TRUE

+1.1V