MRF175LU MRF175LV

6

MOTOROLA RF DEVICE DATA

INPUT AND OUTPUT IMPEDANCE

f = 400 MHz

f = 400 MHz

300

300

100

30

225

30

LOAD IMPEDANCE INTO WHICH THE

DEVICE OUTPUT OPERATES AT A GIVEN

OUTPUT POWER, VOLTAGE AND FREQUENCY.

225

175

150

175

150

100

f

MHz

Ohms

Ohms

30

100

150

175

225

300

400

2.80 - j4.00

1.40 - j2.80

1.10 - j1.90

1.00 - j1.25

0.95 - j0.65

0.95 + j0.20

1.05 + j1.15

3.65 - j1.30

2.60 - j1.50

2.10 - j1.40

1.80 - j1.20

1.50 - j0.80

1.35 - j0.30

1.45 + j0.55

Figure 12.

RF POWER MOSFET CONSIDERATIONS

MOSFET CAPACITANCES

The physical structure of a MOSFET results in capacitors

between the terminals. The metal oxide gate structure deter-

of the FET results in a junction capacitance from drain–to–

sheets. The relationships between the inter–terminal capaci-

tances and those given on data sheets are shown below. The

1. Drain shorted to source and positive voltage at the gate.

2. Positive voltage of the drain in respect to source and zero

volts at the gate. In the latter case the numbers are lower.

However, neither method represents the actual operat-

ing conditions in RF applications.

GATE

SOURCE

DRAIN

LINEARITY AND GAIN CHARACTERISTICS

In addition to the typical IMD and power gain data present-

ed, Figure 3 may give the designer additional information on

the capabilities of this device. The graph represents the

small signal unity current gain frequency at a given drain cur-

Since this test is performed at a fast sweep speed, heating of

the device does not occur. Thus, in normal use, the higher

temperatures may degrade these characteristics to some ex-

tent.

DRAIN CHARACTERISTICS

One figure of merit for a FET is its static resistance in the

linear region of the output characteristic and is specified un-

der specific test conditions for gate–source voltage and drain

coefficient and constitutes an important design consideration

at high temperatures, because it contributes to the power

dissipation within the device.

GATE CHARACTERISTICS

The gate of the FET is a polysilicon material, and is electri-

cally isolated from the source by a layer of oxide. The input

ing in a leakage current of a few nanoamperes.

Gate control is achieved by applying a positive voltage

slightly in excess of the gate–to–source threshold voltage,

Gate Voltage Rating — Never exceed the gate voltage

damage to the oxide layer in the gate region.

Gate Termination — The gates of these devices are es-

sentially capacitors. Circuits that leave the gate open–cir-

cuited or floating should be avoided. These conditions can

result in turn–on of the devices due to voltage build–up on

the input capacitor due to leakage currents or pickup.