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9DB1233 Datasheet(PDF) 2 Page - Integrated Circuit Systems |
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9DB1233 Datasheet(HTML) 2 Page - Integrated Circuit Systems |
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2 / 15 page ![]() IDT® Twelve Output Differential Buffer for PCIe Gen3 9DB1233 Twelve Output Differential Buffer for PCIe Gen3 2 1675B—11/08/10 Pin Configuration VDD 1 64 VDDA DIF_IN 2 63 AGND DIF_IN# 3 62 IREF GND 4 61 VDD OE0# 5 60 OE11# DIF_0 6 59 DIF_11 DIF_0# 7 58 DIF_11# VDD 8 57 VDD GND 9 56 GND OE1# 10 55 OE10# DIF_1 11 54 DIF_10 DIF_1# 12 53 DIF_10# OE2# 13 52 OE9# DIF_2 14 51 DIF_9 DIF_2# 15 50 DIF_9# GND 16 49 GND VDD 17 48 VDD OE3# 18 47 OE8# DIF_3 19 46 DIF_8 DIF_3# 20 45 DIF_8# OE4# 21 44 OE7# DIF_4 22 43 DIF_7 DIF_4# 23 42 DIF_7# VDD 24 41 VDD GND 25 40 GND OE5# 26 39 OE6# DIF_5 27 38 DIF_6 DIF_5# 28 37 DIF_6# **ADR_SEL 29 36 VTTPWRGD#/PD HIGH_BW# 30 35 BYPASS#/PLL VDD 31 34 GND SMBCLK 32 33 SMBDAT 64-TSSOP ** Indicates 120K ohm Pulldown Power Groups VDD GND 1 4 DIF_IN/DIF_IN# 8, 17, 24, 41, 48, 57 9, 16, 25, 40, 49, 56 DIF(11:0) N/A 63 IREF 64 63 Analog VDD & GND for PLL core Note: Please treat pin 1 as an analog VDD. Description Pin Number SMBus Address Selection (Pin 29) ADR_SEL Voltage SMBus Adr (Wr/Rd) Low <0.8V DC/DD Mid 1.2<Vin<1.8V D6/D7 High Vin > 2.0V D4/D5 |
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