9DB1233

Twelve Output Differential Buffer for PCIe Gen3

4

1675B—11/08/10

Pin Description (cont.)

PIN #

PIN NAME

TYPE

DESCRIPTION

33

SMBDAT

I/O

Data pin of SMBUS circuitry, 5V tolerant

34

GND

PWR

Ground pin.

35

BYPASS#/PLL

IN

Input to select Bypass(fan-out) or PLL (ZDB) mode

0 = Bypass mode, 1= PLL mode

36

VTTPWRGD#/PD

IN

VTTPWRGD# is an active low input used to sample latched inputs and

allow the device to Power Up. PD is an asynchronous active high input

pin used to put the device into a low power state. The internal clocks and

PLLs are stopped.

37

DIF_6#

OUT

0.7V differential Complementary clock output

38

DIF_6

OUT

0.7V differential true clock output

39

OE6#

IN

Active low input for enabling DIF pair 6.

1 =disable outputs, 0 = enable outputs

40

GND

PWR

Ground pin.

41

VDD

PWR

Power supply, nominal 3.3V

42

DIF_7#

OUT

0.7V differential Complementary clock output

43

DIF_7

OUT

0.7V differential true clock output

44

OE7#

IN

Active low input for enabling DIF pair 7.

1 =disable outputs, 0 = enable outputs

45

DIF_8#

OUT

0.7V differential Complementary clock output

46

DIF_8

OUT

0.7V differential true clock output

47

OE8#

IN

Active low input for enabling DIF pair 8.

1 =disable outputs, 0 = enable outputs

48

VDD

PWR

Power supply, nominal 3.3V

49

GND

PWR

Ground pin.

50

DIF_9#

OUT

0.7V differential Complementary clock output

51

DIF_9

OUT

0.7V differential true clock output

52

OE9#

IN

Active low input for enabling DIF pair 9.

1 =disable outputs, 0 = enable outputs

53

DIF_10#

OUT

0.7V differential Complementary clock output

54

DIF_10

OUT

0.7V differential true clock output

55

OE10#

IN

Active low input for enabling DIF pair 10.

1 =disable outputs, 0 = enable outputs

56

GND

PWR

Ground pin.

57

VDD

PWR

Power supply, nominal 3.3V

58

DIF_11#

OUT

0.7V differential Complementary clock output

59

DIF_11

OUT

0.7V differential true clock output

60

OE11#

IN

Active low input for enabling DIF pair 11.

1 =disable outputs, 0 = enable outputs

61

VDD

PWR

Power supply, nominal 3.3V

62

IREF

OUT

This pin establishes the reference current for the differential current-

mode output pairs. This pin requires a fixed precision resistor tied to

ground in order to establish the appropriate current. 475 ohms is the

standard value.

63

AGND

PWR

Analog Ground pin for Core PLL

64

VDDA

PWR

3.3V power for the PLL core.