ICS841N254BI datasheet(12/24 Pages) IDT

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ICS841N254BKI REVISION A NOVEMBER 6, 2013

ICS841N254BI Data Sheet

FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER

Applications Information

Recommendations for Unused Input Pins

Inputs:

REF_CLK Input

For applications not requiring the use of the reference clock, it can be

left floating. Though not required, but for additional protection, a 1k



resistor can be tied from the REF_CLK to ground.

Crystal Inputs

For applications not requiring the use of the crystal oscillator input,

both XTAL_IN and XTAL_OUT can be left floating. Though not

required, but for additional protection, a 1k

 resistor can be tied from

XTAL_IN to ground.

LVCMOS Control Pins

All control pins have internal pulldowns; additional resistance is not

required but can be added for additional protection. A 1k

 resistor

can be used.

Outputs:

LVDS Outputs

All unused LVDS output pairs can be either left floating or terminated

with 100

 across. If they are left floating, we recommend that there

is no trace attached.

Differential Outputs

All unused differential outputs can be left floating. We recommend

that there is no trace attached. Both sides of the differential output

pair should either be left floating or terminated.

Interface to IDT S-RIO Switches

The ICS841N254BI is designed for driving the differential reference

clock input (REF_CLK) of IDT’s S-RIO 1.3 and 2.0 switch devices.

Both the LVDS and the HCSL outputs of the ICS841N254BI have the

low-jitter, differential voltage and impedance characteristics required

to provide a high-quality 156.25MHz clock signal for both S-RIO 1.3

and 2.0 switch devices. Please refer to Figure 1A and Figure 1B for

suggested interfaces. The interfaces differ by the driving output,

LVDS and HCSL, and the corresponding source termination method.

In both Figure 1A and 1B, the AC-coupling capacitors are mandatory

by the IDT S-RIO switch devices. The differential REF_CLK input is

internally re-biased and AC-terminated. Both interface circuits are

optimized for 50

 transmission lines and generate the voltage swing

required to reliably drive the clock reference input of a IDT S-RIO

switch. Please refer to IDT’s S-RIO device datasheet for more details.

REF_CLK

ICS841N254BI

IDT S-RIO 1.3, 2.0 Switch

VBIAS

QAn



nQAn

T= 50



LVDS

REF_CLK_P



REF_CLK_N

Figure 1A. LVDS-to-S-RIO 2.0 Reference Clock Interface



Figure 1A shows the recommended interface circuit for driving the

156.25MHz reference clock of an IDT S-RIO 2.0 switch by a LVDS

output (QA0, QA1) of the ICS841N254BI. The LVDS-to-differential

interface as shown in Figure 1A does not require any external

termination resistors: the ICS841N254BI driver contains an internal

source termination at QA0 and QA1. The differential REF_CLK input

contains an internal AC-termination (RL) and re-bias (VBIAS).

Figure 4B shows the interface circuit for driving the 156.25MHz

reference clock of an IDT S-RIO 2.0 switch by an HCSL output of the

ICS841N254BI (QB0, QB1): The HCSL-to-differential interface

requires external termination resistors (22...33

 and 50) for source

termination, which should be placed close the driver (QB0, QB1).

REF_CLK

ICS841N254BI

IDT S-RIO 1.3, 2.0 Switch

VBIAS

REF_CLK_P



REF_CLK_N

QBn



nQBn

T= 50



HCSL

22...33

49.9

22...33

49.9

Figure 1B. HCSL-to-S-RIO 2.0 Reference Clock Interface

ICS841N254BI Datasheet(PDF) 12 Page - Integrated Device Technology

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