1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

7

Rev D 2/17/15

8745B-21 DATA SHEET

AC Electrical Characteristics

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal across all conditions, when

the PLL is locked and the input reference frequency is stable.

NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential

cross points.

NOTE 4: Phase jitter is dependent on the input source used.

NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 6: Characterized at VCO frequency of 622MHz.

NOTE 7: Measured from the 20% to 80% points. Guaranteed by characterization. Not production tested.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Output Frequency

700

MHz

Propagation Delay; NOTE 1

PLL_SEL = 0V, f

 700MHz

3.1

3.4

4.0

ns

tsk(Ø)

Static Phase Offset; NOTE 2, 5

PLL_SEL = 3.3V

-100

25

150

ps

tsk(o)

Output Skew; NOTE 3, 5

35

ps

tjit(cc)

Cycle-to-Cycle Jitter; NOTE 5, 6

30

ps

tjit(

)

Phase Jitter; NOTE 4, 5, 6

±52

ps

PLL Lock Time

1ms

Output Rise/Fall Time; NOTE 7

20% to 80%

200

700

ps

odc

Output Duty Cycle

46

50

54

%