Rev D 2/17/15

16

1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

8745B-21 DATA SHEET

Reliability Information

Transistor Count

The transistor count for 8745B-21 is: 2772

Package Outline and Package Dimensions

Package Outline - M Suffix for 20 Lead SOIC

Table 9. Package Dimensions for 20 Lead SOIC

Reference Document: JEDEC Publication 95, MS-013, MS-119



Linear Feet per Minute

0

200

500

Single-Layer PCB, JEDEC Standard Test Boards

83.2°C/W

65.7°C/W

57.5°C/W

Multi-Layer PCB, JEDEC Standard Test Boards

46.2°C/W

39.7°C/W

36.8°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

300 Millimeters

All Dimensions in Millimeters

Symbol

Minimum

Maximum

N

20

A

2.65

A1

0.10

A2

2.05

2.55

B

0.33

0.51

C

0.18

0.32

D

12.60

13.00

E

7.40

7.60

e

1.27 Basic

H

10.00

10.65

h

0.25

0.75

L

0.40

1.27



0°

7°