8745B-21 datasheet(11/19 Pages) IDT

11 / 19 page

1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

Rev D 2/17/15

8745B-21 DATA SHEET

Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and

other differential signals. Both signals must meet the VPP and VCMR

input requirements. Figures 3A to 3F show interface examples for the

CLK/nCLK input driven by the most common driver types. The input

interfaces suggested here are examples only. Please consult with the

vendor of the driver component to confirm the driver termination

requirements. For example, in Figure 3A, the input termination

applies for IDT open emitter LVHSTL drivers. If you are using an

LVHSTL driver from another vendor, use their termination

recommendation.

3A. CLK/nCLK Input Driven by an

IDT Open Emitter LVHSTL Driver

Figure 3C. CLK/nCLK Input Driven by a

3.3V LVPECL Driver

Figure 3E. CLK/nCLK Input Driven by a

3.3V HCSL Driver

Figure 3B. CLK/nCLK Input Driven by a

3.3V LVPECL Driver

Figure 3D. CLK/nCLK Input Driven by a

3.3V LVDS Driver

Figure 3F. CLK/nCLK Input Driven by a

2.5V SSTL Driver

1.8V

Zo = 50

CLK

nCLK

3.3V

LVHSTL

IDT

LVHSTL Driver

Differential

Input

HCSL

*R3

*R4

CLK

nCLK

3.3V

Differential

Input

CLK

nCLK

Differential

Input

SSTL

2.5V

Zo = 60

2.5V

3.3V

120

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