ULTRA LOW CURRENT CONSUMPTION AND LOW DROPOUT CMOS VOLTAGE REGULATOR

S-1206 Series

Seiko Instruments Inc.

12



Operation

1. Basic Operation

Figure 11

shows the block diagram of the S-1206 Series.

output voltage which is not influenced by the input voltage and temperature change, to the output transistor.

*1

*1. Parasitic diode

VSS

Current

supply

−

+

VIN

VOUT

Error

amplifier

Reference voltage

circuit

Figure 11

2. Output Transistor

In the S-1206 Series, a low on-resistance P-channel MOS FET is used as the output transistor.

+ 0.3 V to prevent the voltage regulator from being damaged due to reverse

3. Overcurrent Protection Circuit

The S-1206 Series includes an overcurrent protection circuit having the characteristics shown in “1. Output Voltage

vs. Output Current (Ta = 25

°C)” in “ Characteristics (Typical Data)”, in order to protect the output transistor

against an excessive output current and short circuiting between the VOUT and VSS pins. The current when the

(typ.)

(2.3 V

once.

Caution This overcurrent protection circuit does not work as for thermal protection. If this IC long keeps

short circuiting inside, pay attention to the conditions of input voltage and load current so that,

under the usage conditions including short circuit, the loss of the IC will not exceed power

dissipation of the package.