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MAX6301ESA Datasheet(PDF) 10 Page - Maxim Integrated Products |
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MAX6301ESA Datasheet(HTML) 10 Page - Maxim Integrated Products |
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10 / 12 page ![]() Ensuring a Valid RESET/RESET Output Down to VCC = 0V (MAX6303/MAX6304) When VCC falls below 1V, RESET/RESET current sink- ing (sourcing) capabilities decline drastically. In the case of the MAX6303, high-impedance CMOS-logic inputs connected to RESET can drift to undetermined voltages. This presents no problem in most applica- tions, since most µPs and other circuitry do not operate with VCC below 1V. In those applications where RESET must be valid down to 0V, adding a pull-down resistor between RESET and ground sinks any stray leakage currents, holding RESET low (Figure 9). The value of the pull-down resis- tor is not critical; 100k Ω is large enough not to load RESET and small enough to pull RESET to ground. For applications using the MAX6304, a 100k Ω pull-up resis- tor between RESET and VCC will hold RESET high when VCC falls below 1V (Figure 10). Watchdog-Software Considerations To help the watchdog timer monitor software execution more closely, set and reset the watchdog input at differ- ent points in the program, rather than “pulsing” the watchdog input high-low-high or low-high-low. This technique avoids a “stuck” loop in which the watchdog timer would continue to be reset within the loop, keep- ing the watchdog from timing out. Figure 11 shows an example of a flow diagram where the I/O driving the watchdog input is set high at the beginning of the program, set low at the beginning of every subroutine or loop, then set high again when the program returns to the beginning. If the program should “hang” in any subroutine the problem would quickly be corrected, since the I/O is continually set low and the watchdog timer is allowed to time out, causing a reset or interrupt to be issued. When using extended mode, as described in the Watchdog Input Current section, this scheme does result in higher average WDI input current than does the method of leaving WDI low for the majority of the timeout period and periodically pulsing it low-high-low. +5V, Low-Power µP Supervisory Circuits with Adjustable Reset/Watchdog 10 ______________________________________________________________________________________ MAX6303 VCC RESET VCC GND 0.1µF 100k Figure 9. Ensuring RESET Valid to VCC = 0V MAX6304 VCC RESET GND VCC 100k 0.1µF Figure 10. Ensuring RESET Valid to VCC = 0V START SET WDI LOW SUBROUTINE OR PROGRAM LOOP SET WDI HIGH RETURN END Figure 11. Watchdog Flow Diagram |
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