SYNC/

SHDN and FREQ Inputs

The SYNC/SHDN pin provides both external-clock syn-

chronization (if desired) and shutdown control. When

SYNC/SHDN is low, all IC functions are shut down. A

logic high at SYNC/SHDN selects operation at a fre-

So a 500kHz operating frequency, for example, is set

Ω.

Rising clock edges on SYNC/SHDN are interpreted as

synchronization inputs. If the sync signal is lost while

SYNC/SHDN is high, the internal oscillator takes over at

the end of the last cycle and the frequency is returned

low, the IC waits for 70µs before shutting down. This

maintains output regulation even with intermittent sync

signals. When an external sync signal is used, Idle

Mode switchover at the 15mV current-sense threshold

is disabled so that Idle Mode only occurs at very light

below the SYNC clock rate:

Soft-Start

The MAX668/MAX669 feature a “digital” soft start which

is preset and requires no external capacitor. Upon

start-up, the peak inductor increments from 1/5 of the

sequence takes 5ms. See the

Typical Operating

start is implemented: 1) when power is first applied to

the IC, 2) when exiting shutdown with power already

applied, and 3) when exiting undervoltage lockout. The

MAX669’s soft-start sequence does not start until LDO

reaches 2.5V.

Design Procedure

The MAX668/MAX669 can operate in a number of DC-

DC converter configurations including step-up, SEPIC

(single-ended primary inductance converter), and fly-

back. The following design discussions are limited to

step-up, although SEPIC and flyback examples are

shown in the

Setting the Operating Frequency

The MAX668/MAX669 can be set to operate from

100kHz to 500kHz. Choice of operating frequency will

depend on number of factors:

1) Noise considerations may dictate setting (or syn-

or band of frequencies, particularly in RF applica-

tions.

2) Higher frequencies allow the use of smaller value

(hence smaller size) inductors and capacitors.

3) Higher frequencies consume more operating power

both to operate the IC and to charge and discharge

the gate of the external FET. This tends to reduce

efficiency at light loads; however, the MAX668/

MAX669’s Idle Mode feature substantially increases

light-load efficiency.

4) Higher frequencies may exhibit poorer overall effi-

ciency due to more transition losses in the FET;

however, this shortcoming can often be nullified by

trading some of the inductor and capacitor size

benefits for lower-resistance components.

is in each case:

when

Setting the Output Voltage

The output voltage is set by two external resistors (R2

and R3, Figures 2, 3, 4, and 5). First select a value for

R3 in the 10k

Ω to 1MΩ range. R2 is then given by:

Determining Inductance Value

For most MAX668/MAX669 boost designs, the inductor

tion, which picks the optimum value for stability based

on the MAX668/MAX669’s internally set slope compen-

sation:

The MAX668/MAX669 allow significant latitude in induc-

be obtained with suitable resistance and saturation-cur-

rent rating in the desired size. Inductance values small-

effects; however, the peak-to-peak inductor current

also requiring larger output capacitance to maintain a

1.8V to 28V Input, PWM Step-Up

Controllers in µMAX

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