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AFE5812 Datasheet(PDF) 39 Page - Texas Instruments |
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AFE5812 Datasheet(HTML) 39 Page - Texas Instruments |
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39 / 109 page ![]() LNA1 Weight Weight Weight Weight LNA2~8 In-phase CLK Quadrature CLK I/V I/V Summed In-Phase Summed Quadrature Syncronized I/Q CLOCKs AFE5812 www.ti.com SLOS816A – MARCH 2015 – REVISED MARCH 2015 Figure 73. Block Diagram of 1 x ƒcw mode 10.3.6 Digital I/Q Demodulator AFE5812 also includes a digital in-phase and quadrature (I/Q) demodulator and a low-pass decimation filter. The main purpose of the demodulation block is to reduce the LVDS data rate and improve overall system power efficiency. The I/Q demodulator accepts ADC output with up to 65 MSPS sampling rate and 14-bit resolution. For example, after digital demodulation and 4× decimation filtering, the data rate for either in-phase or quadrature output is reduced to 16.25 MSPS, and the data resolution is improved to 16 bits consequently. Hence, the overall LVDS trace reduction can be a factor of 2. This demodulator can be bypassed and powered down completely if it is not needed. The digital demodulator block given in AFE5812 is designed to do down-conversion followed by decimation. The top-level block is divided into two exactly similar blocks: (1) subchip0 and (2) subchip1. Both subchips share four channels each, that is, subchip0 (ADC.1, ADC.2, ADC.3, and ADC.4) and subchip1 (ADC.5, ADC.6, ADC.7, and ADC.8). Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 39 Product Folder Links: AFE5812 |
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