AFE5812 datasheet(71/109 Pages) TI

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x = C + 2 sin(

)

AFE5812

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SLOS816A – MARCH 2015 – REVISED MARCH 2015

•

Decimation block can be bypassed using register DEC_BYPASS.

•

Decimation factor: This can be set using the decimation factor (M) parameter of the profile vector.

Alternatively, it can be set using registers MANUAL_DEC_FACTOR_EN and MANUAL_DEC_FACTOR.

•

Filter coefficients: Filter coefficients should be written to coefficient RAM (see Profile RAM and Coefficient

RAM). The format of the filter coefficient is 2’s complement. Its address pointer should be given in profile

vector, or alternatively, registers MANUAL_COEFF_START_EN and MANUAL_COEFF_START_ADDR can

be used.

•

Filter digital gain: Decimation block takes 14-bit input data and 14-bit input coefficients and gives 36-bit output

internally. While implementing this FIR filter, after multiplication and addition, the 36-bit internal filter output

should be scaled approximately to make the final demod output as 16 bit, that is, applying digital gain or

attenuation. Filter gain or attenuation depends on two parameters: decimation shift scale and gain

compensation factor.

•

Decimation shift scale can be chosen using register DEC_SHIFT_SCALE. The gain compensation factor can

be given to the gain compensation factor (G) parameter of the profile vector, or can be given using registers

DEC_SHIFT_FORCE_EN and DEC_SHIFT_FORCE.

•

The internal 36-bit filter output is right-shifted by N bits, where N equals:

–

20-G when Dec_Shift_Scale = 0

–

20-G-2 when Dec_Shift_Scale = 1

The minimal gain occurs when G = 0 and DEC_SHIFT_SCALE = 0. The total scaling range can be a factor of

29, that is, approximately 54 dB.

Table 18. Test Modes

SPI Address

TM_SINE_DC

0x1E[15:9]

TM_SINE_AMP

0x1E[8:5]

TM_SINE_STEP

0x1E[4:0]

TM_SINE_EN

0x1D[2]

TM_COEFF_EN

0x1D[3]

1. Sine test mode:

The normal ADC output can be replaced by:

(5)

–

N is a 5-bit unsigned value, controlling the sine wave frequency with resolution of FS / 2

6, which is 0.625

MHz for 40-MHz ADC clock.

–

k is 4-bit unsigned value, controlling the wave amplitude, from unity to the full scale of 14 bits, including

saturation.

–

C is 7-bit signed value for DC offset control.

The controlling values fit into one 16-bit register. This test pattern shall allow testing of demodulation,

decimation filter, DC removal, gain control, and so on.

2. Coefficient output test mode:

–

The input to the decimating filter can be replaced with a sequence of one impulse and zero samples,

where one impulse (0x4000) is followed by (16 × M) zeros (that is, 0 × 0000).

–

This mode is useful to check decimation filter coefficients.

–

This mode can be enabled using register TM_COEFF_EN.

3. RF mode:

RF mode allows for the streaming of ADC data through the demodulator to the LVDS. Note: Test pattern

from the ADC output stage cannot be sent to the demodulator (it can only be sent to the LVDS when the

demodulator is off). RF mode without sync word can be set by the following:

(a) Configure the ADC Serialization rate as 16bit, by setting ADC register 03[14:13]=01B.

(b) Write

0x0041

demod

0xDF;

that

MANUAL_DEC_FACTOR_EN

and

MANUAL_DEC_FACTOR = 1.

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