CMX983 datasheet(30/93 Pages) CMLMICRO

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Analogue Front End (AFE) for Digital Radio

CMX983

 2015 CML Microsystems Plc

D/983/6

the device inputs, to prevent aliasing problems in the first downsampler. The number of cascaded stages in

the sinc filter can be configured to between 3 and 6, with each stage having a length of up to 64. The length of

the sinc filter should be set to an integer multiple (usually 1x) of the first downsample rate M1 so that the

zeroes in the filter transfer function appear at multiples of the CR2 clock rate. This minimises the amount of

in-band energy in the aliased signals after decimation. Note that the sinc filter transfer characteristic causes

droop in the wanted signal, and this droop increases as the number of sinc stages or the sinc length is

increased. However, moderate amounts of droop can be compensated for in the following FIR filter. With a

nominal power supply voltage (AVDD = 3.3V), the “gain” of the ADC between the input pins and the output of

the sinc filter is given by the expression:

1506



where L = sinc length, N = number of sinc stages and A = analogue gain (see section 9.1). For example, with

an analogue gain of 0dB, a sinc length of 32 and a sinc number of 5, then a dc input signal of 1V (differential)

at the input pins will give a nominal output of 5.053x10

6 (~ $4D1B00) into the first bit selector.

First bit selector

The bit selector at the output of the sinc filter selects which 20 bits of the 37-bit sinc filter accumulator are

passed to the following phase vernier and downsampler.

Phase vernier

The phase vernier allows fine adjustment of the signal phase by setting which sinc output sample the first

decimator selects. The A and B channel signals can be independently delayed by a programmable number of

cycles of the CR1 clock, with the maximum number of delay cycles being one less than the first downsample

rate.

First downsampler

The first downsampler reduces the sample rate of the signal by a factor of M1 = fCR1/fCR2. This process causes

any residual signal components around multiples of the CR2 clock rate to be aliased, so it is important to

make sure that the preceding filters (sinc filter and external anti-alias filter) have adequately attenuated these

signal components.

FIR filter

The purpose of the FIR filter is to attenuate out-of band signals and quantisation noise, perform any transfer

function shaping that is required by the transmission standard and, if necessary, compensate for the droop

caused by the sinc filter. The FIR filter acts as an anti-alias filter for the second downsampler (if used) by

ensuring that signal components around multiples of the CR3 frequency are adequately attenuated. The filter

operates with 20-bit data samples and 16-bit coefficients, and can be configured with up to 128 taps. There

are four banks of programmable coefficients.

Second bit selector

The bit selector at the output of the FIR filter selects which 16 bits of the 42-bit FIR filter accumulator are

passed to the following downsampler.

Second downsampler

The second downsampler reduces the sample rate of the signal by a factor of M2 = fCR2/fCR3. This process

causes any residual signal components around multiples of the CR3 clock rate to be aliased, so it is important

to make sure that the preceding filters have adequately attenuated these signal components.

CMX983 Datasheet(PDF) 30 Page - CML Microcircuits

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