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CMX983 Datasheet(PDF) 71 Page - CML Microcircuits

Part # CMX983
Description  Programmable Channel Filter
PDF  93 Pages
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Manufacturer  CMLMICRO [CML Microcircuits]
Direct Link  http://www.cmlmicro.com
Logo CMLMICRO - CML Microcircuits

CMX983 Datasheet(HTML) 71 Page - CML Microcircuits

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Analogue Front End (AFE) for Digital Radio
CMX983
 2015 CML Microsystems Plc
71
D/983/6
AUXCMP_STAT - $7B: 8-bit Read
Reset value = $00
Bit:
7
6
5
4
3
2
1
0
0
0
0
Cmp
thresh
flag 4
Cmp
thresh
flag 3
Cmp
thresh
flag 2
Cmp
thresh
flag 1
Cmp
thresh
flag 0
AUXCMP_STAT Register b7-5: Reserved, set to 0
AUXCMP_STAT Register b4-0: Comparator threshold flag 4..0
Each comparator threshold flag gets set to 1 if the associated comparator is enabled and the
corresponding input pin voltage is greater than the programmed threshold voltage (or less than, if the
comparator output is inverted). The threshold flags in AUXCMP_STAT are sticky: once they are set to
1 they remain in that state until a C-BUS read of AUXCMP_STAT is performed, after which they are
automatically cleared to 0. When AUXCMP_STAT is read, if the comparator input is still greater than
the programmed threshold voltage then the flag will stay high. Disabling a comparator channel does
not automatically clear the associated flag bit.
The five threshold flags in the AUXCMP_STAT register are gated with the enable bits in the
AUXCMP_STAT_EN register and are then ORed together. The resulting analogue comparator status
bit is passed to the CMX983 STATUS register (section 6.4), as shown in Figure 27. This can be used
to generate an interrupt signal.
Figure 27 Comparator and Threshold Status Flag
AUXCMP_ST_EN - $7C: 8-bit Write
Reset value = $00
Bit:
7
6
5
4
3
2
1
0
0
0
0
Enab
stat 4
Enab
stat 3
Enab
stat 2
Enab
stat 1
Enab
stat 0
AUXCMP_ST_EN Register b7-5: Reserved, set to 0
AUXCMP_ST_EN Register b4-0: Enable status 4..0
Setting any of the enable status bits to 1 allows the associated comparator threshold flag in the
AUXCMP_STAT register to drive the analogue comparator status bit to 1.
+
-
AUXCMP_CON0
bit 7 (Enab cmp)
AUXCMP_CON0
bit 6 (Invert cmp)
AUXCMP_ST_EN
bit 0 (Enab stat 0)
Read
AUXCMP_STAT
AUXCMP_STAT
bit 0
1
2
3
4
Analogue
comparator
status
[Comparator / latch
channel 0 shown]
From channels 1...4
set
rst
Q
CLK



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