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AM1806 Datasheet(PDF) 38 Page - Texas Instruments

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Part # AM1806
Description  AM1806 ARM짰 Microprocessor
PDF  245 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
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AM1806 Datasheet(HTML) 38 Page - Texas Instruments

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AM1806
SPRS658F – FEBRUARY 2010 – REVISED MARCH 2014
www.ti.com
3.7.16 Multichannel Buffered Serial Ports (McBSP)
Table 3-18. Multichannel Buffered Serial Ports (McBSPs) Terminal Functions
SIGNAL
POWER
TYPE(1)
PULL(2)
DESCRIPTION
GROUP(3)
NAME
NO.
McBSP0
AXR0 / ECAP0_APWM0 / GP8[7] / CLKS0
F3
I
CP[6]
A
McBSP0 sample rate generator clock input
AXR6 / CLKR0 / GP1[14] / PRU0_R31[6]
C1
I/O
CP[5]
A
McBSP0 receive clock
AXR4 / FSR0 / GP1[12]
D1
I/O
CP[5]
A
McBSP0 receive frame sync
AXR2 / DR0 / GP1[10]
E2
I
CP[5]
A
McBSP0 receive data
AXR5 / CLKX0 / GP1[13]
D3
I/O
CP[5]
A
McBSP0 transmit clock
AXR3 / FSX0 / GP1[11]
E3
I/O
CP[5]
A
McBSP0 transmit frame sync
AXR1 / DX0 / GP1[9]
E1
O
CP[5]
A
McBSP0 transmit data
McBSP1
AXR8 / CLKS1 / ECAP1_APWM1 / GP0[0] /
E4
I
CP[3]
A
McBSP1 sample rate generator clock input
PRU0_R31[8]
AXR14 / CLKR1 / GP0[6]
B4
I/O
CP[2]
A
McBSP1 receive clock
AXR12 / FSR1 / GP0[4]
C4
I/O
CP[2]
A
McBSP1 receive frame sync
AXR10 / DR1 / GP0[2]
D4
I
CP[2]
A
McBSP1 receive data
AXR13 / CLKX1 / GP0[5]
B3
I/O
CP[2]
A
McBSP1 transmit clock
AXR11 / FSX1 / GP0[3]
C5
I/O
CP[2]
A
McBSP1 transmit frame sync
AXR9 / DX1 / GP0[1]
C3
O
CP[2]
A
McBSP1 transmit data
(1)
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2)
IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the
device is out of reset. During reset, all of the pins associated with these registers are pulled down. If the application requires a pull-up,
an external pull-up can be used. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see the Device Configuration section. For electrical specifications on pullup and internal pulldown
circuits, see the Device Operating Conditions section.
(3)
This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
38
Device Overview
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