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AM1806 Datasheet(PDF) 99 Page - Texas Instruments

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Part # AM1806
Description  AM1806 ARM짰 Microprocessor
PDF  245 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

AM1806 Datasheet(HTML) 99 Page - Texas Instruments

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AM1806
www.ti.com
SPRS658F – FEBRUARY 2010 – REVISED MARCH 2014
Table 6-22. Switching Characteristics for EMIFA Asynchronous Memory Interface (1) (2) (3)
1.3V, 1.2V, 1.1V, 1.0V
NO.
PARAMETER
UNIT
MIN
Nom
MAX
READS and WRITES
1
td(TURNAROUND)
Turn around time
(TA)*E - 3
(TA)*E
(TA)*E + 3
ns
READS
EMIF read cycle time (EW = 0)
(RS+RST+RH)*E - 3
(RS+RST+RH)*E
(RS+RST+RH)*E + 3
ns
3
tc(EMRCYCLE)
EMIF read cycle time (EW = 1)
(RS+RST+RH+EWC)*E - 3
(RS+RST+RH+EWC)*E
(RS+RST+RH+EWC)*E + 3
ns
Output setup time, EMA_CE[5:2] low to EMA_OE low (SS = 0)
(RS)*E-3
(RS)*E
(RS)*E+3
ns
4
tsu(EMCEL-EMOEL)
Output setup time, EMA_CE[5:2] low to EMA_OE low (SS = 1)
-3
0
+3
ns
Output hold time, EMA_OE high to EMA_CE[5:2] high (SS = 0)
(RH)*E - 3
(RH)*E
(RH)*E + 3
ns
5
th(EMOEH-EMCEH)
Output hold time, EMA_OE high to EMA_CE[5:2] high (SS = 1)
-3
0
+3
ns
6
tsu(EMBAV-EMOEL)
Output setup time, EMA_BA[1:0] valid to EMA_OE low
(RS)*E-3
(RS)*E
(RS)*E+3
ns
7
th(EMOEH-EMBAIV)
Output hold time, EMA_OE high to EMA_BA[1:0] invalid
(RH)*E-3
(RH)*E
(RH)*E+3
ns
8
tsu(EMBAV-EMOEL)
Output setup time, EMA_A[13:0] valid to EMA_OE low
(RS)*E-3
(RS)*E
(RS)*E+3
ns
9
th(EMOEH-EMAIV)
Output hold time, EMA_OE high to EMA_A[13:0] invalid
(RH)*E-3
(RH)*E
(RH)*E+3
ns
EMA_OE active low width (EW = 0)
(RST)*E-3
(RST)*E
(RST)*E+3
ns
10
tw(EMOEL)
EMA_OE active low width (EW = 1)
(RST+EWC)*E-3
(RST+EWC)*E
(RST+EWC)*E+3
ns
11
td(EMWAITH-EMOEH)
Delay time from EMA_WAIT deasserted to EMA_OE high
3E-3
4E
4E+3
ns
28
tsu(EMARW-EMOEL)
Output setup time, EMA_A_RW valid to EMA_OE low
(RS)*E-3
(RS)*E
(RS)*E+3
ns
29
th(EMOEH-EMARW)
Output hold time, EMA_OE high to EMA_A_RW invalid
(RH)*E-3
(RH)*E
(RH)*E+3
ns
WRITES
EMIF write cycle time (EW = 0)
(WS+WST+WH)*E-3
(WS+WST+WH)*E
(WS+WST+WH)*E+3
ns
15
tc(EMWCYCLE)
(WS+WST+WH+EWC)*E +
EMIF write cycle time (EW = 1)
(WS+WST+WH+EWC)*E - 3
(WS+WST+WH+EWC)*E
ns
3
Output setup time, EMA_CE[5:2] low to EMA_WE low (SS = 0)
(WS)*E - 3
(WS)*E
(WS)*E + 3
ns
16
tsu(EMCEL-EMWEL)
Output setup time, EMA_CE[5:2] low to EMA_WE low (SS = 1)
-3
0
+3
ns
Output hold time, EMA_WE high to EMA_CE[5:2] high (SS = 0)
(WH)*E-3
(WH)*E
(WH)*E+3
ns
17
th(EMWEH-EMCEH)
Output hold time, EMA_WE high to EMA_CE[5:2] high (SS = 1)
-3
0
+3
ns
18
tsu(EMDQMV-EMWEL)
Output setup time, EMA_BA[1:0] valid to EMA_WE low
(WS)*E-3
(WS)*E
(WS)*E+3
ns
19
th(EMWEH-EMDQMIV)
Output hold time, EMA_WE high to EMA_BA[1:0] invalid
(WH)*E-3
(WH)*E
(WH)*E+3
ns
20
tsu(EMBAV-EMWEL)
Output setup time, EMA_BA[1:0] valid to EMA_WE low
(WS)*E-3
(WS)*E
(WS)*E+3
ns
21
th(EMWEH-EMBAIV)
Output hold time, EMA_WE high to EMA_BA[1:0] invalid
(WH)*E-3
(WH)*E
(WH)*E+3
ns
(1)
TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold, MEWC = Maximum external wait cycles. These
parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle Configuration Registers. These support the following range of values: TA[4-1], RS[16-1], RST[64-
1], RH[8-1], WS[16-1], WST[64-1], WH[8-1], and MEW[1-256].
(2)
E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL0 output clock divided by 4.5. As an example, when SYSCLK3 is selected and set to 100MHz,
E=10ns.
(3)
EWC = external wait cycles determined by EMA_WAIT input signal. EWC supports the following range of values EWC[256-1]. Note that the maximum wait time before timeout is specified
by bit field MEWC in the Asynchronous Wait Cycle Configuration Register.
Copyright © 2010–2014, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
99
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Product Folder Links: AM1806



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