AM1806 datasheet(151/245 Pages) TI

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AM1806

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SPRS658F – FEBRUARY 2010 – REVISED MARCH 2014

Table 6-69. General Timing Requirements for SPI1 Master Modes(1)

1.3V, 1.2V

1.1V

1.0V

NO.

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

tc(SPC)M

Cycle Time, SPI1_CLK, All Master Modes

20(2)

256P

30(2)

256P

40(2)

256P

tw(SPCH)M

Pulse Width High, SPI1_CLK, All Master Modes

0.5M-1

tw(SPCL)M

Pulse Width Low, SPI1_CLK, All Master Modes

0.5M-1

Polarity = 0, Phase = 0,

to SPI1_CLK rising

Polarity = 0, Phase = 1,

-0.5M+5

-0.5M+6

Delay, initial data bit valid on

to SPI1_CLK rising

td(SIMO_SPC)M

SPI1_SIMO to initial edge on

Polarity = 1, Phase = 0,

SPI1_CLK(3)

to SPI1_CLK falling

Polarity = 1, Phase = 1,

-0.5M+5

-0.5M+6

to SPI1_CLK falling

Polarity = 0, Phase = 0,

from SPI1_CLK rising

Polarity = 0, Phase = 1,

Delay, subsequent bits valid on from SPI1_CLK falling

td(SPC_SIMO)M

SPI1_SIMO after transmit edge

Polarity = 1, Phase = 0,

of SPI1_CLK

from SPI1_CLK falling

Polarity = 1, Phase = 1,

from SPI1_CLK rising

Polarity = 0, Phase = 0,

0.5M-3

from SPI1_CLK falling

Polarity = 0, Phase = 1,

0.5M-3

Output hold time, SPI1_SIMO

from SPI1_CLK rising

toh(SPC_SIMO)M

valid after receive edge of

Polarity = 1, Phase = 0,

SPI1_CLK

0.5M-3

from SPI1_CLK rising

Polarity = 1, Phase = 1,

0.5M-3

from SPI1_CLK falling

Polarity = 0, Phase = 0,

1.5

to SPI1_CLK falling

Polarity = 0, Phase = 1,

1.5

Input Setup Time, SPI1_SOMI

to SPI1_CLK rising

tsu(SOMI_SPC)M

valid before receive edge of

Polarity = 1, Phase = 0,

SPI1_CLK

1.5

to SPI1_CLK rising

Polarity = 1, Phase = 1,

1.5

to SPI1_CLK falling

Polarity = 0, Phase = 0,

from SPI1_CLK falling

Polarity = 0, Phase = 1,

Input Hold Time, SPI1_SOMI

from SPI1_CLK rising

tih(SPC_SOMI)M

valid after receive edge of

Polarity = 1, Phase = 0,

SPI1_CLK

from SPI1_CLK rising

Polarity = 1, Phase = 1,

from SPI1_CLK falling

(1)

P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)

(2)

This timing is limited by the timing shown or 3P, whichever is greater.

(3)

First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on

SPI1_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI1_SOMI.

Peripheral Information and Electrical Specifications

151

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