AM4376 datasheet(3/261 Pages) TI

3 / 261 page

AM4376, AM4377, AM4378, AM4379

www.ti.com

SPRS851B – JUNE 2014 – REVISED APRIL 2015

NOR FLASH

–

Four Types of Displays Are Supported:

Passive and Active Colors; Passive and

– One Dallas 1-Wire® and HDQ Serial Interface

Active Monochromes

– Up to Three MMC, SD, and SDIO Ports

–

4- and 8-Bit Monochrome Passive Panel

•

1-, 4-, and 8-Bit MMC, SD, and SDIO Modes

Interface Support (15 Grayscale Levels

•

1.8- or 3.3-V Operation on All Ports

Supported Using Dithering Block)

•

Up to 48-MHz Clock

–

RGB 8-Bit Color Passive Panel Interface

•

Supports Card Detect and Write Protect

Support (3,375 Colors Supported for

•

Complies With MMC4.3 and SD and SDIO

Color Panel Using Dithering Block)

2.0 Specifications

–

RGB 12-, 16-, 18-, and 24-Bit Active

– Up to Three I2C Master and Slave Interfaces

Panel Interface Support (Replicated or

•

Standard Mode (up to 100 kHz)

Dithered Encoded Pixel Values)

•

Fast Mode (up to 400 kHz)

–

Remote Frame Buffer (Embedded in the

LCD Panel) Support Through the RFBI

– Up to Six Banks of General-Purpose I/O (GPIO)

Module

•

32 GPIOs per Bank (Multiplexed With Other

–

Partial Refresh of the Remote Frame

Functional Pins)

Buffer Through the RFBI Module

•

GPIOs Can be Used as Interrupt Inputs (up

–

Partial Display

to Two Interrupt Inputs per Bank)

–

Multiple Cycles Output Format on 8-, 9-,

– Up to Three External DMA Event Inputs That

12-, and 16-Bit Interface (TDM)

Can Also be Used as Interrupt Inputs

•

Signal Processing

– Twelve 32-Bit General-Purpose Timers

–

Overlay and Windowing Support for One

•

DMTIMER1 is a 1-ms Timer Used for

Graphics Layer (RGB or CLUT) and Two

Operating System (OS) Ticks

Video Layers (YUV 4:2:2, RGB16, and

•

DMTIMER4–DMTIMER7 are Pinned Out

RGB24)

– One Public Watchdog Timer

–

RGB 24-Bit Support on the Display

– One Free-Running, High-Resolution 32-kHz

Interface, Optionally Dithered to RGB

Counter (synctimer32K)

‑Bit Pixel Output Plus 6-Bit Frame Rate

– SGX530 3D Graphics Engine

Control (Spatial and Temporal)

•

Tile-Based Architecture Delivering up to 20M

–

Transparency Color Key (Source and

Poly/sec

Destination)

•

Universal Scalable Shader Engine is a

–

Synchronized Buffer Update

Multithreaded Engine Incorporating Pixel and

–

Gamma Curve Support

Vertex Shader Functionality

–

Multiple-Buffer Support

•

Advanced Shader Feature Set in Excess of

–

Cropping Support

Microsoft VS3.0, PS3.0, and OGL2.0

–

Color Phase Rotation

•

Industry Standard API Support of Direct3D

– Two 12-Bit Successive Approximation Register

Mobile, OGL-ES 1.1 and 2.0, and OpenVG

(SAR) ADCs (ADC0, ADC1)

1.0

•

867K Samples Per Second

•

Fine-Grained Task Switching, Load

Balancing, and Power Management

•

Input Can Be Selected from Any of the Eight

Analog Inputs Multiplexed Through an 8:1

•

Advanced Geometry DMA-Driven Operation

Analog Switch

for Minimum CPU Interaction

•

ADC0 Can Be Configured to Operate as a

•

Programmable High-Quality Image Anti-

‑, 5-, or 8-Wire Resistive Touch Screen

Aliasing

Controller (TSC)

•

Fully Virtualized Memory Addressing for OS

– Up to Three 32-Bit eCAP Modules

Operation in a Unified Memory Architecture

•

Configurable as Three Capture Inputs or

– Display Subsystem

Three Auxiliary PWM Outputs

•

Display Modes

– Up to Six Enhanced eHRPWM Modules

–

Programmable Pixel Memory Formats

•

Dedicated 16-Bit Time-Base Counter With

(Palletized: 1-, 2-, 4-, and 8-Bits Per

Time and Frequency Controls

Pixel; RGB 16- and 24-Bits Per Pixel; and

YUV 4:2:2)

•

Configurable as Six Single-Ended, Six Dual-

Edge Symmetric, or Three Dual-Edge

–

256 × 24-Bit Entries Palette in RGB

Asymmetric Outputs

–

Up to 2048 × 2048 Resolution

– Up to Three 32-Bit eQEP Modules

•

Display Support

Device Overview

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