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AM5716 Datasheet(PDF) 16 Page - Texas Instruments |
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AM5716 Datasheet(HTML) 16 Page - Texas Instruments |
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16 / 389 page  AM5716, AM5718 SPRS919I – JUNE 2014 – REVISED OCTOBER 2015 www.ti.com Table 4-2. Ball Characteristics(1) (continued) BALL BALL BALL I/O PULL BALL NUMBER MUXMODE RESET REL. BUFFER BALL NAME [2] SIGNAL NAME [3] 18 / 16 [4] TYPE [6] RESET RESET REL. VOLTAGE POWER [11] HYS [12] UP/DOWN [1] [5] MUXMODE TYPE [13] STATE [7] STATE [8] VALUE [10] TYPE [14] [9] AH25 ddr1_dqs0 ddr1_dqs0 0 IO PD PD 1.35/1.5 vdds_ddr1 NA LVCMOS Pux/PDy DDR AE27 ddr1_dqs1 ddr1_dqs1 0 IO PD PD 1.35/1.5 vdds_ddr1 NA LVCMOS Pux/PDy DDR AD27 ddr1_dqs2 ddr1_dqs2 0 IO PD PD 1.35/1.5 vdds_ddr1 NA LVCMOS Pux/PDy DDR Y28 ddr1_dqs3 ddr1_dqs3 0 IO PD PD 1.35/1.5 vdds_ddr1 NA LVCMOS Pux/PDy DDR AG25 ddr1_dqsn0 ddr1_dqsn0 0 IO PU PU 1.35/1.5 vdds_ddr1 NA LVCMOS Pux/PDy DDR AE28 ddr1_dqsn1 ddr1_dqsn1 0 IO PU PU 1.35/1.5 vdds_ddr1 NA LVCMOS Pux/PDy DDR AD28 ddr1_dqsn2 ddr1_dqsn2 0 IO PU PU 1.35/1.5 vdds_ddr1 NA LVCMOS Pux/PDy DDR Y27 ddr1_dqsn3 ddr1_dqsn3 0 IO PU PU 1.35/1.5 vdds_ddr1 NA LVCMOS Pux/PDy DDR V28 ddr1_dqsn_ecc ddr1_dqsn_ecc 0 IO PU PU 1.35/1.5 vdds_ddr1 NA LVCMOS Pux/PDy DDR V27 ddr1_dqs_ecc ddr1_dqs_ecc 0 IO PD PD 1.35/1.5 vdds_ddr1 NA LVCMOS Pux/PDy DDR W22 ddr1_ecc_d0 ddr1_ecc_d0 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS Pux/PDy DDR V23 ddr1_ecc_d1 ddr1_ecc_d1 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS Pux/PDy DDR W19 ddr1_ecc_d2 ddr1_ecc_d2 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS Pux/PDy DDR W23 ddr1_ecc_d3 ddr1_ecc_d3 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS Pux/PDy DDR Y25 ddr1_ecc_d4 ddr1_ecc_d4 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS Pux/PDy DDR V24 ddr1_ecc_d5 ddr1_ecc_d5 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS Pux/PDy DDR V25 ddr1_ecc_d6 ddr1_ecc_d6 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS Pux/PDy DDR Y26 ddr1_ecc_d7 ddr1_ecc_d7 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS Pux/PDy DDR AH24 ddr1_nck ddr1_nck 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS Pux/PDy DDR AE20 ddr1_odt0 ddr1_odt0 0 O PD drive 0 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS Pux/PDy DDR AC17 ddr1_odt1 ddr1_odt1 0 O PD drive 0 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS Pux/PDy DDR AF20 ddr1_rasn ddr1_rasn 0 O PU drive 1 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS Pux/PDy DDR AG21 ddr1_rst ddr1_rst 0 O PD drive 0 (OFF) 1.35/1.5 vdds_ddr1 No LVCMOS Pux/PDy DDR 16 Terminal Configuration and Functions Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM5716 AM5718 |
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