DM385 datasheet(64/281 Pages) TI

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DM385, DM388

SPRS821D – MARCH 2013 – REVISED DECEMBER 2013

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3.3.2

Boot Configuration

Table 3-13. Boot Configuration Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

BTMODE[0]

Boot Mode Selection 0. ARM Cortex-A8 Boot Mode

Configuration Bits. This pin is multiplexed between ARM

Cortex-A8 boot mode and the General-Purpose Memory

Controller (GPMC) peripheral functions. At reset, the boot

mode inputs BTMODE[4:0] are sampled to determine the

ARM boot configuration. For more details on the types of

boot modes supported, see Section 4.2, Boot Modes, of

this document, along with the ROM Code Memory and

Peripheral Booting chapter of the device Technical

Reference Manual. After reset, this pin functions as

GPMC multiplexed data/address pin 0 (GPMC_D[0]).

BTMODE[1]

Boot Mode Selection 1. ARM Cortex-A8 Boot Mode

Configuration Bits. This pin is multiplexed between ARM

Cortex-A8 boot mode and the General-Purpose Memory

Controller (GPMC) peripheral functions. At reset, the boot

mode inputs BTMODE[4:0] are sampled to determine the

ARM boot configuration. For more details on the types of

boot modes supported, see Section 4.2, Boot Modes, of

this document, along with the ROM Code Memory and

Peripheral Booting chapter of the device Technical

Reference Manual. After reset, this pin functions as

GPMC multiplexed data/address pin 1 (GPMC_D[1]).

BTMODE[2]

Boot Mode Selection 2. ARM Cortex-A8 Boot Mode

Configuration Bits. This pin is multiplexed between ARM

Cortex-A8 boot mode and the General-Purpose Memory

Controller (GPMC) peripheral functions. At reset, the boot

mode inputs BTMODE[4:0] are sampled to determine the

ARM boot configuration. For more details on the types of

boot modes supported, see Section 4.2, Boot Modes, of

this document, along with the ROM Code Memory and

Peripheral Booting chapter of the device Technical

Reference Manual. After reset, this pin functions as

GPMC multiplexed data/address pin 2 (GPMC_D[2]).

BTMODE[3]

Boot Mode Selection 3. ARM Cortex-A8 Boot Mode

Configuration Bits. This pin is multiplexed between ARM

Cortex-A8 boot mode and the General-Purpose Memory

Controller (GPMC) peripheral functions. At reset, the boot

mode inputs BTMODE[4:0] are sampled to determine the

ARM boot configuration. For more details on the types of

boot modes supported, see Section 4.2, Boot Modes, of

this document, along with the ROM Code Memory and

Peripheral Booting chapter of the device Technical

Reference Manual. After reset, this pin functions as

GPMC multiplexed data/address pin 3 (GPMC_D[3]).

BTMODE[4]

Boot Mode Selection 4. ARM Cortex-A8 Boot Mode

Configuration Bits. This pin is multiplexed between ARM

Cortex-A8 boot mode and the General-Purpose Memory

Controller (GPMC) peripheral functions. At reset, the boot

mode inputs BTMODE[4:0] are sampled to determine the

ARM boot configuration. For more details on the types of

boot modes supported, see Section 4.2, Boot Modes, of

this document, along with the ROM Code Memory and

Peripheral Booting chapter of the device Technical

Reference Manual. After reset, this pin functions as

GPMC multiplexed data/address pin 4 (GPMC_D[4]).

BTMODE[5]

Boot Mode Selection 5. Reserved Boot Pin. This pin is

multiplexed between ARM Cortex-A8 boot mode and

General-Purpose Memory Controller (GPMC) peripheral

functions. For proper device operation at reset, this pin

should be externally pulled low. After reset, this pin

functions as GPMC multiplexed data/address pin 5

(GPMC_D[5]).

Device Pins

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