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DM385 Datasheet(PDF) 18 Page - Texas Instruments |
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DM385 Datasheet(HTML) 18 Page - Texas Instruments |
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18 / 281 page  DM385, DM388 SPRS821D – MARCH 2013 – REVISED DECEMBER 2013 www.ti.com 2.10.2.2 L4 Slow Peripheral Memory Map Table 2-5. L4 Slow Peripheral Memory Map Cortex-A8 and L3 Masters SIZE DEVICE NAME START ADDRESS END ADDRESS (HEX) (HEX) 0x4800_0000 0x4800_07FF 2KB L4 Slow Configuration – Address/Protection (AP) 0x4800_0800 0x4800_0FFF 2KB L4 Slow Configuration – Link Agent (LA) 0x4800_1000 0x4800_13FF 1KB L4 Slow Configuration – Initiator Port (IP0) 0x4800_1400 0x4800_17FF 1KB L4 Slow Configuration – Initiator Port (IP1) 0x4800_1800 0x4800_1FFF 2KB Reserved 0x4800_2000 0x4800_7FFF 24KB Reserved 0x4800_8000 0x4800_8FFF 32KB Reserved 0x4801_0000 0x4801_0FFF 4KB Reserved 0x4801_1000 0x4801_1FFF 4KB Reserved 0x4801_2000 0x4801_FFFF 56KB Reserved 0x4802_0000 0x4802_0FFF 4KB UART0 Peripheral Registers 0x4802_1000 0x4802_1FFF 4KB UART0 Interconnect Registers 0x4802_2000 0x4802_2FFF 4KB UART1 Peripheral Registers 0x4802_3000 0x4802_3FFF 4KB UART1 Interconnect Registers 0x4802_4000 0x4802_4FFF 4KB UART2 Peripheral Registers 0x4802_5000 0x4802_5FFF 4KB UART2 Interconnect Registers 0x4802_6000 0x4802_7FFF 8KB Reserved 0x4802_8000 0x4802_8FFF 4KB I2C0 Peripheral Registers 0x4802_9000 0x4802_9FFF 4KB I2C0 Interconnect Registers 0x4802_A000 0x4802_AFFF 4KB I2C1 Peripheral Registers 0x4802_B000 0x4802_BFFF 4KB I2C1 Interconnect Registers 0x4802_C000 0x4802_DFFF 8KB Reserved 0x4802_E000 0x4802_EFFF 4KB TIMER1 Peripheral Registers 0x4802_F000 0x4802_FFFF 4KB TIMER1 Interconnect Registers 0x4803_0000 0x4803_0FFF 4KB SPI0 Peripheral Registers 0x4803_1000 0x4803_1FFF 4KB SPI0 Interconnect Registers 0x4803_2000 0x4803_2FFF 4KB GPIO0 Peripheral Registers 0x4803_3000 0x4803_3FFF 4KB GPIO0 Interconnect Registers 0x4803_4000 0x4803_7FFF 16KB Reserved 0x4803_8000 0x4803_9FFF 8KB McASP0 CFG Peripheral Registers 0x4803_A000 0x4803_AFFF 4KB McASP0 CFG Interconnect Registers 0x4803_B000 0x4803_BFFF 4KB Reserved 0x4803_C000 0x4803_DFFF 8KB McASP1 CFG Peripheral Registers 0x4803_E000 0x4803_EFFF 4KB McASP1 CFG Interconnect Registers 0x4803_F000 0x4803_FFFF 4KB Reserved 0x4804_0000 0x4804_0FFF 4KB TIMER2 Peripheral Registers 0x4804_1000 0x4804_1FFF 4KB TIMER2 Interconnect Registers 0x4804_2000 0x4804_2FFF 4KB TIMER3 Peripheral Registers 0x4804_3000 0x4804_3FFF 4KB TIMER3 Interconnect Registers 0x4804_4000 0x4804_4FFF 4KB TIMER4 Peripheral Registers 0x4804_5000 0x4804_5FFF 4KB TIMER4 Interconnect Registers 0x4804_6000 0x4804_6FFF 4KB TIMER5 Peripheral Registers 0x4804_7000 0x4804_7FFF 4KB TIMER5 Interconnect Registers 18 Device Overview Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DM385 DM388 |
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