DM385 datasheet(172/281 Pages) TI

172 / 281 page

DM385, DM388

SPRS821D – MARCH 2013 – REVISED DECEMBER 2013

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8.6

Ethernet MAC Switch (EMAC SW)

The EMAC SW controls the flow of packet data between the device and two external Ethernet PHYs, with

hardware flow control and quality-of-service (QOS) support. The EMAC SW contains a 3-port gigabit

switch, where one port is internally connected and the other two ports are brought out externally. Each of

the external EMAC ports supports 10Base-T (10 Mbits/second [Mbps]), and 100BaseTX (100 Mbps), in

either half- or full-duplex mode, and 1000BaseT (1000 Mbps) in full-duplex mode.

The EMAC SW controls the flow of packet data from the device to the external PHYs. The EMAC0/1 ports

on the device support four interface modes: Media Independent Interface (MII), Gigabit Media

Independent Interface (GMII), Reduced Media Independent Interface (RMII) and Reduced Gigabit Media

Independent Interface (RGMII). In addition, a single MDIO interface is pinned out to control the PHY

configuration and status monitoring. Multiple external PHYs can be controlled by the MDIO interface.

The EMAC SW module conforms to the IEEE 802.3-2002 standard, describing the “Carrier Sense Multiple

Access with Collision Detection (CSMA/CD) Access Method and Physical Layer” specifications. The IEEE

802.3 standard has also been adopted by ISO/IEC and re-designated as ISO/IEC 8802-3:2000(E).

Deviating from this standard, the EMAC SW module does not use the Transmit Coding Error signal

MTXER. Instead of driving the error pin when an underflow condition occurs on a transmitted frame, the

EMAC SW will intentionally generate an incorrect checksum by inverting the frame CRC, so that the

transmitted frame will be detected as an error by the network. In addition, the EMAC SW I/Os operate at

3.3 V and are not compatible with 2.5-V I/O signaling. Therefore, only Ethernet PHYs with 3.3-V I/O

interface should be used.

In networking systems, packet transmission and reception are critical tasks. The communications port

programming interface (CPPI) protocol maximizes the efficiency of interaction between the host software

and communications modules. The CPPI block contains 2048 words of 32-bit buffer descriptor memory

that holds up to 512 buffer descriptors.

Ethernet port mirroring is not supported internally on this device. This function is supported by using an

external Ethernet repeater.

For more detailed information on the EMAC SW module, see the 3PSW Ethernet Subsystem chapter in

the device-specific Technical Reference Manual.

8.6.1

EMAC Peripheral Register Descriptions

The EMAC peripheral registers are described in the device-specific Technical Reference Manual. Each

the peripherals are in the device memory map (see Section 2.10).

172

Peripheral Information and Timings

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DM385 Datasheet(PDF) 172 Page - Texas Instruments