DM385 datasheet(178/281 Pages) TI

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EMQAC[x]_RGTXC

(at device)

(A)

EMAC[x]_RGTXD[3:0]

(B)

EMAC[x]_RGTXCTL

(B)

1st Half-byte

TXERR

TXEN

2nd Half-byte

Internal RGTXC

RGTXC at device pins

DM385, DM388

SPRS821D – MARCH 2013 – REVISED DECEMBER 2013

www.ti.com

Table 8-22. Switching Characteristics Over Recommended Operating Conditions for EMAC RGMII

Transmit(1)

(see Figure 8-17)

OPP100/OPP120

NO.

PARAMETER

UNIT

Turbo/Nitro

MIN

MAX

tsu(RGTXD-

Setup time, transmit selected signals valid before

Internal delay enabled

1.2

RGTXCH)

EMAC[x]_RGTXC (at device) high/low

th(RGTXCH-

Hold time, transmit selected signals valid after

Internal delay enabled

1.2

RGTXD)

EMAC[x]_RGTXC (at device) high/low

(1)

For RGMII, transmit selected signals include: EMAC[x]_RGTXD[3:0] and EMAC[x]_RGTXCTL.

RGTXC is delayed internally before being driven to the EMAC[x]_RGTXC pin. The internal delay can be enabled or

disabled via the EMAC RGMIIn_ID_MODE register.

Data and control information is transmitted using both edges of the clocks. EMAC[x]_RGTXD[3:0] carries data bits 3-0

on the rising edge of EMAC[x]_RGTXC and data bits 7-4 on the falling edge of EMAC[x]_RGTXC. Similarly,

EMAC[x]_RGTXCTL carries TXEN on rising edge of EMAC[x]_RGTXC and TXERR of falling edge of

EMAC[x]_RGTXC.

Figure 8-17. EMAC Transmit Interface Timing [RGMII Operation]

178

Peripheral Information and Timings

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