MIC502 datasheet(4/11 Pages) MICREL

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MIC502

Micrel

MIC502

166

May 1999

Symbol

Parameter

Condition

Min

Typ

Max

Units

Overtemperature Fault Output

Active (Low) Output Voltage

OL = 2mA

0.3

Off-State Leakage

/OTF = VDD

µA

Note 1.

Exceeding the absolute maximum rating may damage the device.

Note 2.

The device is not guaranteed to function outside its operating rating.

Note 3.

Devices are ESD sensitive. Handling precautions recommended.

Note 4:

Part is functional over this V

DD range; however, it is characterized for operation at 4.5V ≤ VDD ≤ 5.5V and 10.8V ≤ VDD ≤ 13.2V ranges. These

ranges correspond to nominal V

DD of 5V and 12V, respectively.

Note 5.

Guaranteed by design.

Note 6.

OT is guaranteed by design to always be higher than VPWM(max).

Note 7.

Logic time base and PWM frequency. For other values of C

F, f(Hz) = 30Hz

0.1 F

, where C is in

µF.

Timing Diagrams

VOH

VOL

50%

80%

40%

100%

40%

70%

tSTARTUP

tPWM

Output

Duty Cycle

0.7VDD

0.3VDD

VT1

VT2

VSLP

100%

30%

70%

80%

50%

40%

Input

Signal

Range

VOT

VIH

VIL

VOH

VOL

VOUT

VOTF

Figure 1. Typical System Behavior

Note A.

Output duty-cycle is initially determined by V

T1, as it is greater than VT2.

Note B.

PWM duty-cycle follows V

T1 as it increases.

Note C.

T1 drops below VT2. VT2 now determines the output duty-cycle.

Note D.

The PWM duty-cycle follows V

T2 as it increases.

Note E.

Both V

T1 and VT2 decrease below VSLP but above VIL. The device enters sleep mode.

Note F.

The PWM ‘wakes up’ because one of the control inputs (V

T1 in this case) has risen above VWAKE. The startup timer is triggered, forcing OUT

high for 64 clock periods. (V

WAKE = VSLP + VHYST. See “Electrical Characteristics.”)

Note G.

Following the startup interval, the PWM duty-cycle is the higher of V

T1 and VT2.

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