GS3490

Final Data Sheet

Rev. 1

GENDOC-058568

April 2014

18 of 22

Proprietary & Confidential

www.semtech.com

5. Application Information

5.1 Typical Application Circuit

Figure 5-1: GS3490 Typical Application Circuit

5.2 PCB Layout

Special attention must be paid to component layout when designing Serial Digital

Interfaces for HDTV. A FR-4 dielectric can be used, however, controlled impedance

transmission lines are required for PCB traces longer than approximately 1cm. Note the

following PCB artwork features used to optimize performance:

•

PCB trace width for 3Gb/s rate signals is closely matched to SMT component width

to minimize reflections due to change in trace impedance.

•

High-speed traces are curved to minimize impedance changes.

Cutouts in the inner layers should be used under the GS3490 input and output

components to minimize parasitic capacitance. For more detail on this and other layout

recommendations, please refer to A Guide For Designing With Semtech's 3G-SDI

Equalizers (Doc ID: GENDOC-055280).

SDI/O

750

Ω

470nF

137

Ω

4.7µF

1µF

10nF

7.5nH

1µF

75

Ω

VCC

VCC

100

Ω

75

Ω

VCC

75

Ω

U2

3

2

6

7

27

30

10

9

8.2nH

4.7µF

GS3490

CD

29

CD_ENABLE

28

EQ_DISABLE

RSET

DDO

DDO

DDI

DDI

16

CD_SD_EN

15

EQ_OP_CTL

14

EQ_SQ_ADJ

13

EQ_BYPASS

AGC-

AGC+

SDI

SDI

SDO

SDO

10nF

10nF

10nF

10nF

75

Ω

Note: AC-coupling capacitors may be required on DDI/DDI and DDO/DDO

when interfacing to devices with incompatible common mode voltages.

18

19

23

22

8.2nH

8

EQ_GAIN_SEL