PIC18F010 datasheet(105/176 Pages) MICROCHIP

105 / 176 page

 2001 Microchip Technology Inc.

Preliminary

DS41142A-page 103

PIC18F010/020

ANDWF

AND WREG with f

Syntax:

[ label ] ANDWF

f [ ,d [,a] ]

Operands:

≤ f ≤ 255

∈ [0,1]

Operation:

(WREG) .AND. (f)

→ dest

Status Affected:

N,Z

Encoding:

0001

01da

ffff

Description:

The contents of WREG are AND’ed

with register 'f'. If 'd' is 0, the result

is stored in WREG. If 'd' is 1, the

result is stored back in register 'f'

(default). If ’a’ is 0, the Access

Bank will be selected. If ’a’ is 1, the

bank will be selected as per the

BSR value.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Process

Data

Write to

destination

Example:

ANDWF

REG,

Before Instruction

WREG

0x17

REG

0xC2

After Instruction

WREG

0x02

REG

0xC2

Branch if Carry

Syntax:

[ label ] BC

Operands:

-128

≤ n ≤ 127

Operation:

if carry bit is ’1’

(PC) + 2 + 2n

→ PC

Status Affected:

None

Encoding:

1110

0010

nnnn

Description:

If the Carry bit is ’1’, then the pro-

gram will branch.

The 2’s complement number ’2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

Words:

Cycles:

1(2)

Q Cycle Activity:

If Jump:

Decode

Read literal

’n’

Process

Data

Write to PC

operation

If No Jump:

Decode

Read literal

’n’

Process

Data

operation

Example:

HERE

Before Instruction

address (HERE)

After Instruction

If Carry

address (HERE+12)

If Carry

address (HERE+2)

PIC18F010 Datasheet(PDF) 105 Page - Microchip Technology

PIC18F010 Datasheet(HTML) 105 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL