PIC18F010 datasheet(121/176 Pages) MICROCHIP

121 / 176 page

 2001 Microchip Technology Inc.

Preliminary

DS41142A-page 119

PIC18F010/020

LFSR

Load FSR

Syntax:

[ label ]

LFSR f,k

Operands:

≤ f ≤ 2

≤ k ≤ 4095

Operation:

→ FSRf

Status Affected:

None

Encoding:

1110

1111

1110

0000

00ff

k7kkk

k11kkk

kkkk

Description:

The 12-bit literal ’k’ is loaded into

the file select register pointed to

by ’f’

Words:

Cycles:

Q Cycle Activity:

Decode

Read literal

’k’ MSB

Process

Data

Write

literal ’k’

MSB to

FSRfH

Decode

Read literal

’k’ LSB

Process

Data

Write literal

’k’ to FSRfL

Example:

LFSR FSR2, 0x3AB

After Instruction

FSR2H

0x03

FSR2L

0xAB

MOVF

Move f

Syntax:

[ label ]

MOVF f [ ,d [,a] ]

Operands:

≤ f ≤ 255

∈ [0,1]

Operation:

→ dest

Status Affected:

N,Z

Encoding:

0101

00da

ffff

Description:

The contents of register ’f’ is moved

to a destination dependent upon

the status of ’d’. If 'd' is 0, the result

is placed in WREG. If 'd' is 1, the

result is placed back in register 'f'

(default). Location 'f' can be any-

where in the 256 byte Bank. If ’a’ is

0, the Access Bank will be

selected, overriding the BSR value.

If ’a’ is 1, the Bank will be selected

as per the BSR value.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Process

Data

Write

WREG

Example:

MOVF

REG, W

Before Instruction

REG

0x22

WREG

0xFF

After Instruction

REG

0x22

WREG

0x22

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