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PIC18F010 Datasheet(PDF) 170 Page - Microchip Technology |
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PIC18F010 Datasheet(HTML) 170 Page - Microchip Technology |
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170 / 176 page ![]() PIC18F010/020 DS41142A-page 168 Preliminary 2001 Microchip Technology Inc. S SETF ................................................................................ 129 SLEEP .................................................................. 83, 90, 130 Software Simulator (MPLAB SIM) .................................... 140 Special Features of the CPU .............................................. 83 Special Function Registers ................................................ 31 Stack Full/Underflow Resets .............................................. 27 STATUS Register ............................................................... 40 STKPTR - Stack Pointer Register ...................................... 26 SUBFWB .................................................................. 130, 131 SUBLW ............................................................................ 131 SUBWF ............................................................................ 132 SUBWFB .......................................................................... 133 SWAPF ............................................................................ 134 T TABLAT - Table Latch Register ......................................... 53 Table Read/Write Instructions ............................................ 47 Table Reads/Table Writes .................................................. 30 TBLPTR - Table Pointer Register ...................................... 53 TBLRD ............................................................................. 135 TBLWT ............................................................................. 136 Timer0 Clock Source Edge Select (T0SE Bit) ........................ 75 Clock Source Select (T0CS Bit) ................................. 75 Overflow Interrupt ...................................................... 75 Prescaler. See Prescaler, Timer0 TIMER0 Control Register ................................................... 73 Timing Diagrams Brown-out Reset ...................................................... 154 CLKOUT and I/O ...................................................... 153 CLKOUT and I/O Timing .......................................... 153 External Clock Timing .............................................. 152 Power-up Timer ....................................................... 154 RESET ..................................................................... 154 Slow Rise Time (MCLR Tied to VDD) ......................... 21 Start-up Timer .......................................................... 154 Time-out Sequence on Power-up (Case 1) ............... 20 Time-out Sequence on Power-up (MCLR Not Tied to VDD) - Case 2 ...................................... 20 Time-out Sequence on Power-up (MCLR Tied to VDD) ........................................................... 20 Transition Between Internal Oscillator and OSC1 (EC) ............................................................. 11 Transition from External Oscillator to Internal Oscillator ................................................... 11 Wake-up from SLEEP via Interrupt ............................ 91 Watchdog Timer ....................................................... 154 TMR0 Interrupt ................................................................... 66 Top-of-Stack Access .......................................................... 25 TSTFSZ ........................................................................... 137 Two-Speed Clock Start-up Mode ....................................... 10 Two-Word Instructions ....................................................... 30 W Wake-up from SLEEP .................................................. 83, 90 Timing Diagram ......................................................... 91 Watchdog Timer (WDT) ............................................... 83, 88 Block Diagram ........................................................... 89 Control Register ......................................................... 88 Postscaler. See Postscaler, WDT Programming Considerations .................................... 88 Time-out Period ......................................................... 88 WDTCON Register ............................................................ 88 Weak Pull-up Register ....................................................... 70 Writing to the Data EEPROM Memory .............................. 45 WWW, On-Line Support ...................................................... 2 X XORLW ............................................................................ 137 XORWF ........................................................................... 138 |
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