LP2983_15 datasheet(2/18 Pages) TI

2 / 18 page

J-A

T (MAX) T

P(MAX)

LP2983

SNVS170C – OCTOBER 2001 – REVISED APRIL 2013

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Connection Diagram

Figure 1. 5-Lead Small Outline Package (SOT-23)

Pin Functions

Pin Descriptions

Function

Number

VIN

Input Voltage

GND

Common Ground (device substrate)

ON/OFF

Logic high enable input

ESR

Low side connection for low-ESR output capacitors

VOUT

Regulated Output Voltage

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings

(1)

Storage Temperature Range

−65°C to +150°C

Operating Junction Temperature Range

−40°C to +125°C

Lead Temp. (Soldering, 5 sec.)

260°C

ESD Rating (2)

2 kV

Power Dissipation (3)

Internally Limited

Input Supply Voltage (Survival)

−0.3V to +16V

Input Supply Voltage (Operating)

2.2V to +16V

Shutdown Input Voltage (Survival)

−0.3V to +16V

Output Voltage Survival, (4)

−0.3V to +9V

IOUT (Survival)

Short Circuit Protected

Input-Output Voltage Survival,(5)

−0.3V to +16V

(1)

“Absolute Maximum Ratings” indicate limits beyond which damage to the component may occur. Electrical specifications do not apply

when operating the device outside of its rated operating conditions.

(2)

The ESD rating of pin 3 is 1 kV.

(3)

The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal

resistance,

θJ-A, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperture is calculated

using:

Where the value of

θJ-A for the SOT-23 package is 240°C/W in a typical PC board mounting. Exceeding the maximum allowable

dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown.

(4)

If used in a dual-supply system where the regulator load is returned to a negative supply, the LP2983 output must be diode-clamped to

ground.

(5)

The output PNP structure contains a diode between the VIN to VOUT terminals that is normally reverse-biased. Reversing the polarity

from VIN to VOUT will turn on this diode and possibly cause a destructive latch-up condition (see Application Hints).

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