TC1784 datasheet(95/123 Pages) INFINEON

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TC1784

Electrical ParametersAC Parameters

Data Sheet

V 1.1.1, 2014-05

5.3.4

Phase Locked Loop (PLL)

Phase Locked Loop Operation

When PLL operation is enabled and configured, the PLL clock fVCO (and with it the LMB-

Bus clock fLMB) is constantly adjusted to the selected frequency. The PLL is constantly

adjusting its output frequency to correspond to the input frequency (from crystal or clock

source), resulting in an accumulated jitter that is limited. This means that the relative

deviation for periods of more than one clock cycle is lower than for a single clock cycle.

This is especially important for bus cycles using wait states and for the operation of

timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train

generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter

is negligible.

Two formulas are defined for the (absolute) approximate maximum value of jitter Dm in

[ns] dependent on the K2 - factor, the LMB clock frequency fLMB in [MHz], and the

number m of consecutive fLMB clock periods.

(6)

(7)

With rising number m of clock cycles the maximum jitter increases linearly up to a value

of m that is defined by the K2-factor of the PLL. Beyond this value of m the maximum

Table 25

PLL_SysClk Parameters

Parameter

Symbol

Values

Unit

Note /

Test Condition

Min.

Typ.

Max.

Accumulated Jitter

DP CC

-7

−

7ns

PLL base frequency

fPLLBASE

200

320

MHz

VCO input frequency

fREF CC 8

−

MHz

VCO frequency range

fVCO CC 400

−

720

MHz

PLL lock-in time

tL CC

−

200

μsN > 32

−

400

μsN ≤ 32

for

100

≤

()

and

LMB MHz

[]

() 2

⁄

≤

()

Dmns

[]

740

LMB MHz

[]

---------------------------------------------

⎝⎠

⎛⎞

10 01

–

()

–

()

LMB MHz

[] 1

–

----------------------------------------------------------------

001

⎝⎠

⎛⎞

else

Dmns

[]

740

LMB MHz

[]

---------------------------------------------

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