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Version 3 – May 2014

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3.2 Communication Timings

Default conditions of 25 °C and 1.8 V supply voltage apply to values in the table below, unless otherwise stated.

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units Comments

SCL clock frequency

-

0

-

400

kHz -

Hold time (repeated) START

condition

After this period, the first

clock pulse is generated

0.6

-

-

µs

-

-

1.3

-

-

µs

-

-

0.6

-

-

µs

-

Set-up time for a repeated

START condition

-

0.6

-

-

µs

-

SDA hold time

-

0

-

-

-

-

SDA set-up time

-

100

-

-

ns

-

SCL/SDA rise time

-

20

-

300

ns

-

SCL/SDA fall time

-

20 *

-

300

ns

-

SDA valid time

-

-

-

0.9

µs

-

Set-up time for STOP

condition

-

0.6

-

-

µs

-

Capacitive load on bus line

-

-

-

400

pF

-

Figure 5 Timing diagram for digital input/output pads. SDA directions are seen from the sensor. Bold SDA lines are controlled by the

sensor, plain SDA lines are controlled by the micro-controller. Note that SDA valid read time is triggered by falling edge of preceding toggle.

SCL

70%

30%

SDA

70%

30%

DATA IN

SDA

70%

30%

DATA OUT