KAI-1010 datasheet(3/27 Pages) ONSEMI

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KAI−1010

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DEVICE DESCRIPTION

Architecture

Figure 2. Functional Block Diagram

fV2

fV1

4 Dark Lines at Bottom of Image

2 Dark Lines at Top of Imate

Horizontal Register A

6 Dummies

2 Dummies

Horizontal Register B

VOUTA

VOUTB

H1A

H1B

VDD

VSS/OG

VRD

WELL

VSUB

fV2

fV1

KAI−1010

Active Image Area

1008 (H)

× 1018 (V)

9.0

mm × 9.0 mm Pixels

The KAI−1010 consists of 1024

× 1024 photodiodes,

1024 vertical (parallel) CCD shift registers (VCCDs), and

dual 1032 pixel horizontal (serial) CCD shift registers

(HCCDs) with independent output structures. The device

can be operated in either single or dual line mode. The

advanced, progressive-scan architecture of the device

allows the entire image area to be read out in a single scan.

The active pixels are arranged in a 1008 (H)

× 1018 (V) array

with an additional 16 columns and 6 rows of light-shielded

dark reference pixels.

Image Acquisition

An electronic representation of an image is formed when

incident photons falling on the sensor plane create

electron-hole

pairs

within

the

individual

silicon

photodiodes. These photoelectrons are collected locally by

the formation of potential wells at each photosite. Below

photodiode saturation, the number of photoelectrons

collected at each pixel is linearly dependent on light level

and exposure time and non-linearly dependent on

wavelength. When the photodiode’s charge capacity is

reached, excess electrons are discharged into the substrate to

prevent blooming.

Charge Transport

The accumulated or integrated charge from each

photodiode is transported to the output by a three step

process. The charge is first transported from the photodiodes

to the VCCDs by applying a large positive voltage to the

phase-one vertical clock (

fV1). This reads out every row, or

line, of photodiodes into the VCCDs.

The charge is then transported from the VCCDs to the

HCCDs line by line. Finally, the HCCDs transport these

rows of charge packets to the output structures pixel by

pixel. On each falling edge of the horizontal clock,

fH2,

these charge packets are dumped over the output gate (OG,

Figure 4) onto the floating diffusion (FDA and FDB,

Figure 4).

Both the horizontal and vertical shift registers use

traditional two-phase complementary clocking for charge

transport. Transfer to the HCCDs begins when

fV2 is

clocked high and then low (while holding

fH1A high)

causing charge to be transferred from

fV1 to fV2 and

subsequently into the A HCCD. The A register can now be

read out in single line mode. If it is desired to operate the

device in a dual line readout mode for higher frame rates, this

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