LC87F6D64A

No.A1007-13/19

2. SIO1 Serial I/O Characteristics (Note 4-2-1)

Parameter

Symbol

Pin/

Remarks

Conditions

Specification

VDD[V]

min

typ

max

unit

Frequency

tSCK(3)

SCK1(P15)

See Fig. 6.

2.5 to 5.5

2

tCYC

Low level

pulse width

tSCKL(3)

1

High level

pulse width

tSCKH(3)

1

Frequency

tSCK(4)

SCK1(P15)

• CMOS output selected

• See Fig. 6.

2.5 to 5.5

2

Low level

pulse width

tSCKL(4)

1/2

tSCK

High level

pulse width

tSCKH(4)

1/2

Data setup time

tsDI(2)

SB1(P14),

SI1(P14)

• Must be specified with

respect to rising edge of

SIOCLK.

• See Fig. 6.

2.5 to 5.5

0.03

μs

Data hold time

thDI(2)

2.5 to 5.5

0.03

Output delay time

tdD0(4)

SO1(P13),

SB1(P14)

• Must be specified with

respect to falling edge of

SIOCLK.

• Must be specified as the

time to the beginning of

output state change in

open drain output mode.

• See Fig. 6.

2.5 to 5.5

(1/3)tCYC

+0.05

Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.

Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = 0V

Parameter

Symbol

Pin/Remarks

Conditions

Specification

VDD[V]

min

typ

max

unit

High/low level

pulse width

tPIH(1)

tPIL(1)

INT0(P70),

INT1(P71),

INT2(P16)

• Interrupt acceptable

• Events to timer 0, 1 can be input.

2.5 to 5.5

1

tCYC

tPIH(2)

tPIL(2)

INT3(P17)

(Noise rejection ratio

set to 1/1.)

• Interrupt acceptable

• Events to timer 0 can be input.

2.5 to 5.5

2

tPIH(3)

tPIL(3)

INT3(P17)

(Noise rejection ratio

set to 1/32.)

• Interrupt acceptable

• Events to timer 0 can be input.

2.5 to 5.5

64

tPIH(4)

tPIL(4)

INT3(P17)

(Noise rejection ratio

set to 1/128.)

• Interrupt acceptable

• Events to timer 0 can be input.

2.5 to 5.5

256

tPIL(5)

RES

Reset possible

2.5 to 5.5

200

μs